Commit d022f330 authored by aohui.li's avatar aohui.li

LIS2DW12支持振动唤醒

parent ce5843c9
build/
sdkconfig.old
*.code-workspace
.vscode
.history/
managed_components
.cache/
\ No newline at end of file
...@@ -2,11 +2,13 @@ ...@@ -2,11 +2,13 @@
"C_Cpp.intelliSenseEngine": "default", "C_Cpp.intelliSenseEngine": "default",
"idf.espIdfPath": "/Users/cn/esp/esp-idf", "idf.espIdfPath": "/Users/cn/esp/esp-idf",
"idf.toolsPath": "/Users/cn/.espressif", "idf.toolsPath": "/Users/cn/.espressif",
"idf.pythonInstallPath": "/opt/homebrew/bin/python3", "idf.pythonInstallPath": "/Users/cn/anaconda3/bin/python",
"idf.customExtraVars": { "idf.customExtraVars": {
"IDF_TARGET": "esp32c3" "IDF_TARGET": "esp32c3"
}, },
"idf.openOcdConfigs": [ "idf.openOcdConfigs": [
"board/esp32c3-builtin.cfg" "board/esp32c3-builtin.cfg"
] ],
"idf.port": "/dev/tty.usbserial-11130",
"idf.flashType": "UART"
} }
file(GLOB_RECURSE ALGORITHM_SOURCES ${CMAKE_CURRENT_LIST_DIR}/./*.c)
set(include_dirs ${CMAKE_CURRENT_LIST_DIR}/./)
idf_component_register(SRCS ${ALGORITHM_SOURCES}
INCLUDE_DIRS ${include_dirs})
\ No newline at end of file
## Contributing guide
This document serves as a checklist before contributing to this repository. It includes links to additional information if topics are unclear to you.
This guide mainly focuses on the proper use of Git.
### 1. Before opening an issue
To report a bug/request please enter the issue in the right repository.
Please check the following boxes before posting an issue:
- [ ] `Make sure you are using the latest commit (major releases are Tagged, but corrections are available as new commits).`
- [ ] `Make sure your issue is a question/feedback/suggestion RELATED TO the software provided in this repository.` Otherwise, it should be discussed on the [ST Community forum](https://community.st.com/s/).
- [ ] `Make sure your issue is not already reported/fixed on GitHub or discussed in a previous issue.` Please refer to the tab issue for the list of issues and pull-requests. Do not forget to browse to the **closed** issues.
### 2. Posting the issue
When you have checked the previous boxes, you will find two templates (Bug Report or Other Issue) available in the **Issues** tab of the repository.
### 3. Pull Requests
STMicroelectronics is happy to receive contributions from the community, based on an initial Contributor License Agreement (CLA) procedure.
* If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an Individual CLA (https://cla.st.com).
* If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a Corporate CLA (https://cla.st.com) mentioning your GitHub account name.
* If you are not sure that a CLA (Individual or Corporate) has been signed for your GitHub account, you can check here (https://cla.st.com).
Please note that:
* The Corporate CLA will always take precedence over the Individual CLA.
* One CLA submission is sufficient for any project proposed by STMicroelectronics.
#### How to proceed
* We recommend to engage first a communication through an issue, in order to present your proposal and just to confirm that it corresponds to a STMicroelectronics domain or scope.
* Then fork the project to your GitHub account to further develop your contribution. Please use the latest commit version.
* Please submit one Pull Request for one new feature or proposal. This will facilitate the analysis and the final merge if accepted.
BSD 3-Clause License
Copyright (c) 2019, STMicroelectronics
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/lis2dw12-pid.svg?color=brightgreen)
# 1 - Introduction
Sensor driver for LIS2DW12 sensor written in C programming language. This repository contains the sensor driver files (.h and .c) to be included, or linked directly as a git submodule, in your project. The driver is MISRA compliant and the documentation can be generated using the [Doxygen](http://www.doxygen.org/) tool.
In order to `clone` the complete content of the repository folder, use the command:
```
git clone https://github.com/STMicroelectronics/LIS2DW12-PID/
```
Some examples of driver usage can be found [here](https://github.com/STMicroelectronics/STMems_Standard_C_drivers).
------
# 2 - Integration details
The driver is platform-independent, you only need to define two functions for read and write transactions from the sensor hardware bus (ie. SPI or I²C) and an optional one to implement a delay of millisecond granularity. **A few devices integrate an extra bit in the communication protocol in order to enable multi read/write access, this bit must be managed in the read and write functions defined by the user.** Please refer to the read and write implementation in the [reference examples](https://github.com/STMicroelectronics/STMems_Standard_C_drivers/tree/master/lis2dw12_STdC/examples).
### 2.a Source code integration
- Include in your project the driver files of the sensor (.h and .c)
- Define in your code the read and write functions that use the I²C or SPI platform driver like the following:
```
/** Please note that is MANDATORY: return 0 -> no Error.**/
int32_t platform_write(void *handle, uint8_t reg, const uint8_t *bufp, uint16_t len)
int32_t platform_read(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len)
/** Optional (may be required by driver) **/
void platform_delay(uint32_t millisec)
```
- Declare and initialize the structure of the device interface:
```
xxxxxxx_ctx_t dev_ctx; /** xxxxxxx is the used part number **/
dev_ctx.write_reg = platform_write;
dev_ctx.read_reg = platform_read;
dev_ctx.mdelay = platform_delay;
```
- If needed by the platform read and write functions, initialize the handle parameter:
```
dev_ctx.handle = &platform_handle;
```
Some integration examples can be found [here](https://github.com/STMicroelectronics/STMems_Standard_C_drivers/tree/master/lis2dw12_STdC/examples).
### 2.b Required properties
> - A standard C language compiler for the target MCU
> - A C library for the target MCU and the desired interface (ie. SPI, I²C)
------
**More Information: [http://www.st.com](http://st.com/MEMS)**
**Copyright (C) 2021 STMicroelectronics**
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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
<head>
<meta charset="utf-8" />
<meta name="generator" content="pandoc" />
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
<title>Release Notes for LIS2DW12 Component</title>
<style type="text/css">
code{white-space: pre-wrap;}
span.smallcaps{font-variant: small-caps;}
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<div class="row">
<div class="col-sm-12 col-lg-4">
<center>
<h1 id="release-notes-for-lis2dw12-component-driver">Release Notes for LIS2DW12 Component Driver</h1>
<p>Copyright © 2021 STMicroelectronics<br />
</p>
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
</center>
<h1 id="license">License</h1>
<p>This software component is licensed by ST under BSD 3-Clause license, the “License”. You may not use this component except in compliance with the License. You may obtain a copy of the License at:</p>
<p><a href="https://opensource.org/licenses/BSD-3-Clause">BSD 3-Clause license</a></p>
<h1 id="purpose">Purpose</h1>
<p>This directory contains the LIS2DW12 component drivers.</p>
</div>
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update history</h1>
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 18-June-2021</label>
<div>
<h2 id="main-changes">Main changes</h2>
<h3 id="first-release">First release</h3>
<ul>
<li>First official release [ref. DS v8.0]</li>
</ul>
<h2 id="section"></h2>
</div>
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 18-May-2023</label>
<div>
<h2 id="main-changes-1">Main changes</h2>
<h3 id="section-1"></h3>
<ul>
<li>Fix wrong comment for two ff APIs</li>
<li>Add __weak directive to read/write registers routines</li>
<li>Extend stmdev_ctx_t structure with mdelay callback</li>
<li>repo name changed adding ‘-pid’ extension.</li>
</ul>
<h2 id="section-2"></h2>
</div>
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V2.0.0 / 20-Mar-2024</label>
<div>
<h2 id="main-changes-2">Main changes</h2>
<h3 id="section-3"></h3>
<ul>
<li>Fixed code style (Artistic Style Version 3.4.13)</li>
<li>Add “const” to ctx arg for all APIs</li>
</ul>
<h2 id="section-4"></h2>
</div>
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V2.0.1 / 20-Jun-2024</label>
<div>
<h2 id="main-changes-3">Main changes</h2>
<h3 id="section-5"></h3>
<ul>
<li>updated README.md file with tag reference and mdelay description</li>
</ul>
<h2 id="section-6"></h2>
</div>
<input type="checkbox" id="collapse-section5" checked aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V2.1.0 / 07-Jul-2025</label>
<div>
<h2 id="main-changes-4">Main changes</h2>
<h3 id="section-7"></h3>
<ul>
<li>Fix driver formatting options</li>
<li>Added pointer to private data in stmdev_ctx_t</li>
</ul>
<h2 id="section-8"></h2>
</div>
</div>
</div>
</div>
<footer class="sticky">
<div class="columns">
<div class="column" style="width:95%;">
<p>For complete documentation on LIS2DW12, visit: <a href="https://www.st.com/content/st_com/en/products/mems-and-sensors/accelerometers/lis2dw12.html">LIS2DW12</a></p>
</div><div class="column" style="width:5%;">
<p><abbr title="Based on template cx566953 version 2.0">Info</abbr></p>
</div>
</div>
</footer>
</body>
</html>
---
pagetitle: Release Notes for LIS2DW12 Component
lang: en
header-includes: <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
---
::: {.row}
::: {.col-sm-12 .col-lg-4}
<center>
# Release Notes for LIS2DW12 Component Driver
Copyright &copy; 2021 STMicroelectronics\
[![ST logo](_htmresc/st_logo_2020.png)](https://www.st.com){.logo}
</center>
# License
This software component is licensed by ST under BSD 3-Clause license, the "License".
You may not use this component except in compliance with the License. You may obtain a copy of the License at:
[BSD 3-Clause license](https://opensource.org/licenses/BSD-3-Clause)
# Purpose
This directory contains the LIS2DW12 component drivers.
:::
::: {.col-sm-12 .col-lg-8}
# Update history
::: {.collapse}
<input type="checkbox" id="collapse-section1" aria-hidden="true">
<label for="collapse-section1" aria-hidden="true">V1.0.0 / 18-June-2021</label>
<div>
## Main changes
### First release
- First official release [ref. DS v8.0]
##
</div>
<input type="checkbox" id="collapse-section2" aria-hidden="true">
<label for="collapse-section2" aria-hidden="true">V1.1.0 / 18-May-2023</label>
<div>
## Main changes
###
- Fix wrong comment for two ff APIs
- Add __weak directive to read/write registers routines
- Extend stmdev_ctx_t structure with mdelay callback
- repo name changed adding '-pid' extension.
##
</div>
<input type="checkbox" id="collapse-section3" aria-hidden="true">
<label for="collapse-section3" aria-hidden="true">V2.0.0 / 20-Mar-2024</label>
<div>
## Main changes
###
- Fixed code style (Artistic Style Version 3.4.13)
- Add "const" to ctx arg for all APIs
##
</div>
<input type="checkbox" id="collapse-section4" aria-hidden="true">
<label for="collapse-section4" aria-hidden="true">V2.0.1 / 20-Jun-2024</label>
<div>
## Main changes
###
- updated README.md file with tag reference and mdelay description
##
</div>
<input type="checkbox" id="collapse-section5" checked aria-hidden="true">
<label for="collapse-section5" aria-hidden="true">V2.1.0 / 07-Jul-2025</label>
<div>
## Main changes
###
- Fix driver formatting options
- Added pointer to private data in stmdev_ctx_t
##
</div>
:::
:::
:::
<footer class="sticky">
::: {.columns}
::: {.column width="95%"}
For complete documentation on LIS2DW12,
visit:
[LIS2DW12](https://www.st.com/content/st_com/en/products/mems-and-sensors/accelerometers/lis2dw12.html)
:::
::: {.column width="5%"}
<abbr title="Based on template cx566953 version 2.0">Info</abbr>
:::
:::
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margin-left: 50%; }
.col-md-8,
.row.cols-md-8 > * {
max-width: 66.6666666667%;
flex-basis: 66.6666666667%; }
.col-md-offset-7 {
margin-left: 58.3333333333%; }
.col-md-9,
.row.cols-md-9 > * {
max-width: 75%;
flex-basis: 75%; }
.col-md-offset-8 {
margin-left: 66.6666666667%; }
.col-md-10,
.row.cols-md-10 > * {
max-width: 83.3333333333%;
flex-basis: 83.3333333333%; }
.col-md-offset-9 {
margin-left: 75%; }
.col-md-11,
.row.cols-md-11 > * {
max-width: 91.6666666667%;
flex-basis: 91.6666666667%; }
.col-md-offset-10 {
margin-left: 83.3333333333%; }
.col-md-12,
.row.cols-md-12 > * {
max-width: 100%;
flex-basis: 100%; }
.col-md-offset-11 {
margin-left: 91.6666666667%; }
.col-md-normal {
order: initial; }
.col-md-first {
order: -999; }
.col-md-last {
order: 999; } }
@media screen and (min-width: 1280px) {
.col-lg,
[class^='col-lg-'],
[class^='col-lg-offset-'],
.row[class*='cols-lg-'] > * {
box-sizing: border-box;
flex: 0 0 auto;
padding: 0 calc(var(--universal-padding) / 2); }
.col-lg,
.row.cols-lg > * {
max-width: 100%;
flex-grow: 1;
flex-basis: 0; }
.col-lg-1,
.row.cols-lg-1 > * {
max-width: 8.3333333333%;
flex-basis: 8.3333333333%; }
.col-lg-offset-0 {
margin-left: 0; }
.col-lg-2,
.row.cols-lg-2 > * {
max-width: 16.6666666667%;
flex-basis: 16.6666666667%; }
.col-lg-offset-1 {
margin-left: 8.3333333333%; }
.col-lg-3,
.row.cols-lg-3 > * {
max-width: 25%;
flex-basis: 25%; }
.col-lg-offset-2 {
margin-left: 16.6666666667%; }
.col-lg-4,
.row.cols-lg-4 > * {
max-width: 33.3333333333%;
flex-basis: 33.3333333333%; }
.col-lg-offset-3 {
margin-left: 25%; }
.col-lg-5,
.row.cols-lg-5 > * {
max-width: 41.6666666667%;
flex-basis: 41.6666666667%; }
.col-lg-offset-4 {
margin-left: 33.3333333333%; }
.col-lg-6,
.row.cols-lg-6 > * {
max-width: 50%;
flex-basis: 50%; }
.col-lg-offset-5 {
margin-left: 41.6666666667%; }
.col-lg-7,
.row.cols-lg-7 > * {
max-width: 58.3333333333%;
flex-basis: 58.3333333333%; }
.col-lg-offset-6 {
margin-left: 50%; }
.col-lg-8,
.row.cols-lg-8 > * {
max-width: 66.6666666667%;
flex-basis: 66.6666666667%; }
.col-lg-offset-7 {
margin-left: 58.3333333333%; }
.col-lg-9,
.row.cols-lg-9 > * {
max-width: 75%;
flex-basis: 75%; }
.col-lg-offset-8 {
margin-left: 66.6666666667%; }
.col-lg-10,
.row.cols-lg-10 > * {
max-width: 83.3333333333%;
flex-basis: 83.3333333333%; }
.col-lg-offset-9 {
margin-left: 75%; }
.col-lg-11,
.row.cols-lg-11 > * {
max-width: 91.6666666667%;
flex-basis: 91.6666666667%; }
.col-lg-offset-10 {
margin-left: 83.3333333333%; }
.col-lg-12,
.row.cols-lg-12 > * {
max-width: 100%;
flex-basis: 100%; }
.col-lg-offset-11 {
margin-left: 91.6666666667%; }
.col-lg-normal {
order: initial; }
.col-lg-first {
order: -999; }
.col-lg-last {
order: 999; } }
/* Card component CSS variable definitions */
:root {
--card-back-color: #3cb4e6;
--card-fore-color: #03234b;
--card-border-color: #03234b; }
.card {
display: flex;
flex-direction: column;
justify-content: space-between;
align-self: center;
position: relative;
width: 100%;
background: var(--card-back-color);
color: var(--card-fore-color);
border: 0.0714285714rem solid var(--card-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin);
overflow: hidden; }
@media screen and (min-width: 320px) {
.card {
max-width: 320px; } }
.card > .sectione {
background: var(--card-back-color);
color: var(--card-fore-color);
box-sizing: border-box;
margin: 0;
border: 0;
border-radius: 0;
border-bottom: 0.0714285714rem solid var(--card-border-color);
padding: var(--universal-padding);
width: 100%; }
.card > .sectione.media {
height: 200px;
padding: 0;
-o-object-fit: cover;
object-fit: cover; }
.card > .sectione:last-child {
border-bottom: 0; }
/*
Custom elements for card elements.
*/
@media screen and (min-width: 240px) {
.card.small {
max-width: 240px; } }
@media screen and (min-width: 480px) {
.card.large {
max-width: 480px; } }
.card.fluid {
max-width: 100%;
width: auto; }
.card.warning {
--card-back-color: #e5b8b7;
--card-fore-color: #3b234b;
--card-border-color: #8c0078; }
.card.error {
--card-back-color: #464650;
--card-fore-color: #ffffff;
--card-border-color: #8c0078; }
.card > .sectione.dark {
--card-back-color: #3b234b;
--card-fore-color: #ffffff; }
.card > .sectione.double-padded {
padding: calc(1.5 * var(--universal-padding)); }
/*
Definitions for forms and input elements.
*/
/* Input_control module CSS variable definitions */
:root {
--form-back-color: #ffe97f;
--form-fore-color: #03234b;
--form-border-color: #3cb4e6;
--input-back-color: #ffffff;
--input-fore-color: #03234b;
--input-border-color: #3cb4e6;
--input-focus-color: #0288d1;
--input-invalid-color: #d32f2f;
--button-back-color: #e2e2e2;
--button-hover-back-color: #dcdcdc;
--button-fore-color: #212121;
--button-border-color: transparent;
--button-hover-border-color: transparent;
--button-group-border-color: rgba(124, 124, 124, 0.54); }
form {
background: var(--form-back-color);
color: var(--form-fore-color);
border: 0.0714285714rem solid var(--form-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin);
padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
fieldset {
border: 0.0714285714rem solid var(--form-border-color);
border-radius: var(--universal-border-radius);
margin: calc(var(--universal-margin) / 4);
padding: var(--universal-padding); }
legend {
box-sizing: border-box;
display: table;
max-width: 100%;
white-space: normal;
font-weight: 500;
padding: calc(var(--universal-padding) / 2); }
label {
padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
.input-group {
display: inline-block; }
.input-group.fluid {
display: flex;
align-items: center;
justify-content: center; }
.input-group.fluid > input {
max-width: 100%;
flex-grow: 1;
flex-basis: 0px; }
@media screen and (max-width: 499px) {
.input-group.fluid {
align-items: stretch;
flex-direction: column; } }
.input-group.vertical {
display: flex;
align-items: stretch;
flex-direction: column; }
.input-group.vertical > input {
max-width: 100%;
flex-grow: 1;
flex-basis: 0px; }
[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
height: auto; }
[type="search"] {
-webkit-appearance: textfield;
outline-offset: -2px; }
[type="search"]::-webkit-search-cancel-button,
[type="search"]::-webkit-search-decoration {
-webkit-appearance: none; }
input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
box-sizing: border-box;
background: var(--input-back-color);
color: var(--input-fore-color);
border: 0.0714285714rem solid var(--input-border-color);
border-radius: var(--universal-border-radius);
margin: calc(var(--universal-margin) / 2);
padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
border-color: var(--input-focus-color);
box-shadow: none; }
input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
border-color: var(--input-invalid-color);
box-shadow: none; }
input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
background: var(--secondary-back-color); }
select {
max-width: 100%; }
option {
overflow: hidden;
text-overflow: ellipsis; }
[type="checkbox"], [type="radio"] {
-webkit-appearance: none;
-moz-appearance: none;
appearance: none;
position: relative;
height: calc(1rem + var(--universal-padding) / 2);
width: calc(1rem + var(--universal-padding) / 2);
vertical-align: text-bottom;
padding: 0;
flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
flex-grow: 0 !important; }
[type="checkbox"]:checked:before, [type="radio"]:checked:before {
position: absolute; }
[type="checkbox"]:checked:before {
content: '\2713';
font-family: sans-serif;
font-size: calc(1rem + var(--universal-padding) / 2);
top: calc(0rem - var(--universal-padding));
left: calc(var(--universal-padding) / 4); }
[type="radio"] {
border-radius: 100%; }
[type="radio"]:checked:before {
border-radius: 100%;
content: '';
top: calc(0.0714285714rem + var(--universal-padding) / 2);
left: calc(0.0714285714rem + var(--universal-padding) / 2);
background: var(--input-fore-color);
width: 0.5rem;
height: 0.5rem; }
:placeholder-shown {
color: var(--input-fore-color); }
::-ms-placeholder {
color: var(--input-fore-color);
opacity: 0.54; }
button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
border-style: none;
padding: 0; }
button, html [type="button"], [type="reset"], [type="submit"] {
-webkit-appearance: button; }
button {
overflow: visible;
text-transform: none; }
button, [type="button"], [type="submit"], [type="reset"],
a.button, label.button, .button,
a[role="button"], label[role="button"], [role="button"] {
display: inline-block;
background: var(--button-back-color);
color: var(--button-fore-color);
border: 0.0714285714rem solid var(--button-border-color);
border-radius: var(--universal-border-radius);
padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
margin: var(--universal-margin);
text-decoration: none;
cursor: pointer;
transition: background 0.3s; }
button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
a.button:hover,
a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
a[role="button"]:hover,
a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
background: var(--button-hover-back-color);
border-color: var(--button-hover-border-color); }
input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
cursor: not-allowed;
opacity: 0.75; }
.button-group {
display: flex;
border: 0.0714285714rem solid var(--button-group-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin); }
.button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
margin: 0;
max-width: 100%;
flex: 1 1 auto;
text-align: center;
border: 0;
border-radius: 0;
box-shadow: none; }
.button-group > :not(:first-child) {
border-left: 0.0714285714rem solid var(--button-group-border-color); }
@media screen and (max-width: 499px) {
.button-group {
flex-direction: column; }
.button-group > :not(:first-child) {
border: 0;
border-top: 0.0714285714rem solid var(--button-group-border-color); } }
/*
Custom elements for forms and input elements.
*/
button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
--button-back-color: #1976d2;
--button-fore-color: #f8f8f8; }
button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
--button-hover-back-color: #1565c0; }
button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
--button-back-color: #d32f2f;
--button-fore-color: #f8f8f8; }
button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
--button-hover-back-color: #c62828; }
button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
--button-back-color: #308732;
--button-fore-color: #f8f8f8; }
button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
--button-hover-back-color: #277529; }
button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
--button-back-color: #212121;
--button-fore-color: #f8f8f8; }
button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
--button-hover-back-color: #111; }
button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
margin: var(--universal-margin); }
button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
margin: var(--universal-margin); }
/*
Definitions for navigation elements.
*/
/* Navigation module CSS variable definitions */
:root {
--header-back-color: #03234b;
--header-hover-back-color: #ffd200;
--header-fore-color: #ffffff;
--header-border-color: #3cb4e6;
--nav-back-color: #ffffff;
--nav-hover-back-color: #ffe97f;
--nav-fore-color: #e6007e;
--nav-border-color: #3cb4e6;
--nav-link-color: #3cb4e6;
--footer-fore-color: #ffffff;
--footer-back-color: #03234b;
--footer-border-color: #3cb4e6;
--footer-link-color: #3cb4e6;
--drawer-back-color: #ffffff;
--drawer-hover-back-color: #ffe97f;
--drawer-border-color: #3cb4e6;
--drawer-close-color: #e6007e; }
header {
height: 2.75rem;
background: var(--header-back-color);
color: var(--header-fore-color);
border-bottom: 0.0714285714rem solid var(--header-border-color);
padding: calc(var(--universal-padding) / 4) 0;
white-space: nowrap;
overflow-x: auto;
overflow-y: hidden; }
header.row {
box-sizing: content-box; }
header .logo {
color: var(--header-fore-color);
font-size: 1.75rem;
padding: var(--universal-padding) calc(2 * var(--universal-padding));
text-decoration: none; }
header button, header [type="button"], header .button, header [role="button"] {
box-sizing: border-box;
position: relative;
top: calc(0rem - var(--universal-padding) / 4);
height: calc(3.1875rem + var(--universal-padding) / 2);
background: var(--header-back-color);
line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
text-align: center;
color: var(--header-fore-color);
border: 0;
border-radius: 0;
margin: 0;
text-transform: uppercase; }
header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
background: var(--header-hover-back-color); }
nav {
background: var(--nav-back-color);
color: var(--nav-fore-color);
border: 0.0714285714rem solid var(--nav-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin); }
nav * {
padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
nav a, nav a:visited {
display: block;
color: var(--nav-link-color);
border-radius: var(--universal-border-radius);
transition: background 0.3s; }
nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
text-decoration: none;
background: var(--nav-hover-back-color); }
nav .sublink-1 {
position: relative;
margin-left: calc(2 * var(--universal-padding)); }
nav .sublink-1:before {
position: absolute;
left: calc(var(--universal-padding) - 1 * var(--universal-padding));
top: -0.0714285714rem;
content: '';
height: 100%;
border: 0.0714285714rem solid var(--nav-border-color);
border-left: 0; }
nav .sublink-2 {
position: relative;
margin-left: calc(4 * var(--universal-padding)); }
nav .sublink-2:before {
position: absolute;
left: calc(var(--universal-padding) - 3 * var(--universal-padding));
top: -0.0714285714rem;
content: '';
height: 100%;
border: 0.0714285714rem solid var(--nav-border-color);
border-left: 0; }
footer {
background: var(--footer-back-color);
color: var(--footer-fore-color);
border-top: 0.0714285714rem solid var(--footer-border-color);
padding: calc(2 * var(--universal-padding)) var(--universal-padding);
font-size: 0.875rem; }
footer a, footer a:visited {
color: var(--footer-link-color); }
header.sticky {
position: -webkit-sticky;
position: sticky;
z-index: 1101;
top: 0; }
footer.sticky {
position: -webkit-sticky;
position: sticky;
z-index: 1101;
bottom: 0; }
.drawer-toggle:before {
display: inline-block;
position: relative;
vertical-align: bottom;
content: '\00a0\2261\00a0';
font-family: sans-serif;
font-size: 1.5em; }
@media screen and (min-width: 500px) {
.drawer-toggle:not(.persistent) {
display: none; } }
[type="checkbox"].drawer {
height: 1px;
width: 1px;
margin: -1px;
overflow: hidden;
position: absolute;
clip: rect(0 0 0 0);
-webkit-clip-path: inset(100%);
clip-path: inset(100%); }
[type="checkbox"].drawer + * {
display: block;
box-sizing: border-box;
position: fixed;
top: 0;
width: 320px;
height: 100vh;
overflow-y: auto;
background: var(--drawer-back-color);
border: 0.0714285714rem solid var(--drawer-border-color);
border-radius: 0;
margin: 0;
z-index: 1110;
right: -320px;
transition: right 0.3s; }
[type="checkbox"].drawer + * .drawer-close {
position: absolute;
top: var(--universal-margin);
right: var(--universal-margin);
z-index: 1111;
width: 2rem;
height: 2rem;
border-radius: var(--universal-border-radius);
padding: var(--universal-padding);
margin: 0;
cursor: pointer;
transition: background 0.3s; }
[type="checkbox"].drawer + * .drawer-close:before {
display: block;
content: '\00D7';
color: var(--drawer-close-color);
position: relative;
font-family: sans-serif;
font-size: 2rem;
line-height: 1;
text-align: center; }
[type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
background: var(--drawer-hover-back-color); }
@media screen and (max-width: 320px) {
[type="checkbox"].drawer + * {
width: 100%; } }
[type="checkbox"].drawer:checked + * {
right: 0; }
@media screen and (min-width: 500px) {
[type="checkbox"].drawer:not(.persistent) + * {
position: static;
height: 100%;
z-index: 1100; }
[type="checkbox"].drawer:not(.persistent) + * .drawer-close {
display: none; } }
/*
Definitions for the responsive table component.
*/
/* Table module CSS variable definitions. */
:root {
--table-border-color: #03234b;
--table-border-separator-color: #03234b;
--table-head-back-color: #03234b;
--table-head-fore-color: #ffffff;
--table-body-back-color: #ffffff;
--table-body-fore-color: #03234b;
--table-body-alt-back-color: #f4f4f4; }
table {
border-collapse: separate;
border-spacing: 0;
margin: 0;
display: flex;
flex: 0 1 auto;
flex-flow: row wrap;
padding: var(--universal-padding);
padding-top: 0; }
table caption {
font-size: 1rem;
margin: calc(2 * var(--universal-margin)) 0;
max-width: 100%;
flex: 0 0 100%; }
table thead, table tbody {
display: flex;
flex-flow: row wrap;
border: 0.0714285714rem solid var(--table-border-color); }
table thead {
z-index: 999;
border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }
table tbody {
border-top: 0;
margin-top: calc(0 - var(--universal-margin));
border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
table tr {
display: flex;
padding: 0; }
table th, table td {
padding: calc(0.5 * var(--universal-padding));
font-size: 0.9rem; }
table th {
text-align: left;
background: var(--table-head-back-color);
color: var(--table-head-fore-color); }
table td {
background: var(--table-body-back-color);
color: var(--table-body-fore-color);
border-top: 0.0714285714rem solid var(--table-border-color); }
table:not(.horizontal) {
overflow: auto;
max-height: 100%; }
table:not(.horizontal) thead, table:not(.horizontal) tbody {
max-width: 100%;
flex: 0 0 100%; }
table:not(.horizontal) tr {
flex-flow: row wrap;
flex: 0 0 100%; }
table:not(.horizontal) th, table:not(.horizontal) td {
flex: 1 0 0%;
overflow: hidden;
text-overflow: ellipsis; }
table:not(.horizontal) thead {
position: sticky;
top: 0; }
table:not(.horizontal) tbody tr:first-child td {
border-top: 0; }
table.horizontal {
border: 0; }
table.horizontal thead, table.horizontal tbody {
border: 0;
flex: .2 0 0;
flex-flow: row nowrap; }
table.horizontal tbody {
overflow: auto;
justify-content: space-between;
flex: .8 0 0;
margin-left: 0;
padding-bottom: calc(var(--universal-padding) / 4); }
table.horizontal tr {
flex-direction: column;
flex: 1 0 auto; }
table.horizontal th, table.horizontal td {
width: auto;
border: 0;
border-bottom: 0.0714285714rem solid var(--table-border-color); }
table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
border-top: 0; }
table.horizontal th {
text-align: right;
border-left: 0.0714285714rem solid var(--table-border-color);
border-right: 0.0714285714rem solid var(--table-border-separator-color); }
table.horizontal thead tr:first-child {
padding-left: 0; }
table.horizontal th:first-child, table.horizontal td:first-child {
border-top: 0.0714285714rem solid var(--table-border-color); }
table.horizontal tbody tr:last-child td {
border-right: 0.0714285714rem solid var(--table-border-color); }
table.horizontal tbody tr:last-child td:first-child {
border-top-right-radius: 0.25rem; }
table.horizontal tbody tr:last-child td:last-child {
border-bottom-right-radius: 0.25rem; }
table.horizontal thead tr:first-child th:first-child {
border-top-left-radius: 0.25rem; }
table.horizontal thead tr:first-child th:last-child {
border-bottom-left-radius: 0.25rem; }
@media screen and (max-width: 499px) {
table, table.horizontal {
border-collapse: collapse;
border: 0;
width: 100%;
display: table; }
table thead, table th, table.horizontal thead, table.horizontal th {
border: 0;
height: 1px;
width: 1px;
margin: -1px;
overflow: hidden;
padding: 0;
position: absolute;
clip: rect(0 0 0 0);
-webkit-clip-path: inset(100%);
clip-path: inset(100%); }
table tbody, table.horizontal tbody {
border: 0;
display: table-row-group; }
table tr, table.horizontal tr {
display: block;
border: 0.0714285714rem solid var(--table-border-color);
border-radius: var(--universal-border-radius);
background: #ffffff;
padding: var(--universal-padding);
margin: var(--universal-margin);
margin-bottom: calc(1 * var(--universal-margin)); }
table th, table td, table.horizontal th, table.horizontal td {
width: auto; }
table td, table.horizontal td {
display: block;
border: 0;
text-align: right; }
table td:before, table.horizontal td:before {
content: attr(data-label);
float: left;
font-weight: 600; }
table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
border-top: 0; }
table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
border-right: 0; } }
table tr:nth-of-type(2n) > td {
background: var(--table-body-alt-back-color); }
@media screen and (max-width: 500px) {
table tr:nth-of-type(2n) {
background: var(--table-body-alt-back-color); } }
:root {
--table-body-hover-back-color: #90caf9; }
table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
background: var(--table-body-hover-back-color); }
@media screen and (max-width: 500px) {
table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
background: var(--table-body-hover-back-color); } }
/*
Definitions for contextual background elements, toasts and tooltips.
*/
/* Contextual module CSS variable definitions */
:root {
--mark-back-color: #3cb4e6;
--mark-fore-color: #ffffff; }
mark {
background: var(--mark-back-color);
color: var(--mark-fore-color);
font-size: 0.95em;
line-height: 1em;
border-radius: var(--universal-border-radius);
padding: calc(var(--universal-padding) / 4) var(--universal-padding); }
mark.inline-block {
display: inline-block;
font-size: 1em;
line-height: 1.4;
padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
:root {
--toast-back-color: #424242;
--toast-fore-color: #fafafa; }
.toast {
position: fixed;
bottom: calc(var(--universal-margin) * 3);
left: 50%;
transform: translate(-50%, -50%);
z-index: 1111;
color: var(--toast-fore-color);
background: var(--toast-back-color);
border-radius: calc(var(--universal-border-radius) * 16);
padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
:root {
--tooltip-back-color: #212121;
--tooltip-fore-color: #fafafa; }
.tooltip {
position: relative;
display: inline-block; }
.tooltip:before, .tooltip:after {
position: absolute;
opacity: 0;
clip: rect(0 0 0 0);
-webkit-clip-path: inset(100%);
clip-path: inset(100%);
transition: all 0.3s;
z-index: 1010;
left: 50%; }
.tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
bottom: 75%; }
.tooltip.bottom:before, .tooltip.bottom:after {
top: 75%; }
.tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
opacity: 1;
clip: auto;
-webkit-clip-path: inset(0%);
clip-path: inset(0%); }
.tooltip:before {
content: '';
background: transparent;
border: var(--universal-margin) solid transparent;
left: calc(50% - var(--universal-margin)); }
.tooltip:not(.bottom):before {
border-top-color: #212121; }
.tooltip.bottom:before {
border-bottom-color: #212121; }
.tooltip:after {
content: attr(aria-label);
color: var(--tooltip-fore-color);
background: var(--tooltip-back-color);
border-radius: var(--universal-border-radius);
padding: var(--universal-padding);
white-space: nowrap;
transform: translateX(-50%); }
.tooltip:not(.bottom):after {
margin-bottom: calc(2 * var(--universal-margin)); }
.tooltip.bottom:after {
margin-top: calc(2 * var(--universal-margin)); }
:root {
--modal-overlay-color: rgba(0, 0, 0, 0.45);
--modal-close-color: #e6007e;
--modal-close-hover-color: #ffe97f; }
[type="checkbox"].modal {
height: 1px;
width: 1px;
margin: -1px;
overflow: hidden;
position: absolute;
clip: rect(0 0 0 0);
-webkit-clip-path: inset(100%);
clip-path: inset(100%); }
[type="checkbox"].modal + div {
position: fixed;
top: 0;
left: 0;
display: none;
width: 100vw;
height: 100vh;
background: var(--modal-overlay-color); }
[type="checkbox"].modal + div .card {
margin: 0 auto;
max-height: 50vh;
overflow: auto; }
[type="checkbox"].modal + div .card .modal-close {
position: absolute;
top: 0;
right: 0;
width: 1.75rem;
height: 1.75rem;
border-radius: var(--universal-border-radius);
padding: var(--universal-padding);
margin: 0;
cursor: pointer;
transition: background 0.3s; }
[type="checkbox"].modal + div .card .modal-close:before {
display: block;
content: '\00D7';
color: var(--modal-close-color);
position: relative;
font-family: sans-serif;
font-size: 1.75rem;
line-height: 1;
text-align: center; }
[type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
background: var(--modal-close-hover-color); }
[type="checkbox"].modal:checked + div {
display: flex;
flex: 0 1 auto;
z-index: 1200; }
[type="checkbox"].modal:checked + div .card .modal-close {
z-index: 1211; }
:root {
--collapse-label-back-color: #03234b;
--collapse-label-fore-color: #ffffff;
--collapse-label-hover-back-color: #3cb4e6;
--collapse-selected-label-back-color: #3cb4e6;
--collapse-border-color: var(--collapse-label-back-color);
--collapse-selected-border-color: #ceecf8;
--collapse-content-back-color: #ffffff;
--collapse-selected-label-border-color: #3cb4e6; }
.collapse {
width: calc(100% - 2 * var(--universal-margin));
opacity: 1;
display: flex;
flex-direction: column;
margin: var(--universal-margin);
border-radius: var(--universal-border-radius); }
.collapse > [type="radio"], .collapse > [type="checkbox"] {
height: 1px;
width: 1px;
margin: -1px;
overflow: hidden;
position: absolute;
clip: rect(0 0 0 0);
-webkit-clip-path: inset(100%);
clip-path: inset(100%); }
.collapse > label {
flex-grow: 1;
display: inline-block;
height: 1.25rem;
cursor: pointer;
transition: background 0.2s;
color: var(--collapse-label-fore-color);
background: var(--collapse-label-back-color);
border: 0.0714285714rem solid var(--collapse-selected-border-color);
padding: calc(1.25 * var(--universal-padding)); }
.collapse > label:hover, .collapse > label:focus {
background: var(--collapse-label-hover-back-color); }
.collapse > label + div {
flex-basis: auto;
height: 1px;
width: 1px;
margin: -1px;
overflow: hidden;
position: absolute;
clip: rect(0 0 0 0);
-webkit-clip-path: inset(100%);
clip-path: inset(100%);
transition: max-height 0.3s;
max-height: 1px; }
.collapse > :checked + label {
background: var(--collapse-selected-label-back-color);
border-color: var(--collapse-selected-label-border-color); }
.collapse > :checked + label + div {
box-sizing: border-box;
position: relative;
width: 100%;
height: auto;
overflow: auto;
margin: 0;
background: var(--collapse-content-back-color);
border: 0.0714285714rem solid var(--collapse-selected-border-color);
border-top: 0;
padding: var(--universal-padding);
clip: auto;
-webkit-clip-path: inset(0%);
clip-path: inset(0%);
max-height: 100%; }
.collapse > label:not(:first-of-type) {
border-top: 0; }
.collapse > label:first-of-type {
border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
.collapse > label:last-of-type:not(:first-of-type) {
border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
.collapse > label:last-of-type:first-of-type {
border-radius: var(--universal-border-radius); }
.collapse > :checked:last-of-type:not(:first-of-type) + label {
border-radius: 0; }
.collapse > :checked:last-of-type + label + div {
border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
/*
Custom elements for contextual background elements, toasts and tooltips.
*/
mark.tertiary {
--mark-back-color: #3cb4e6; }
mark.tag {
padding: calc(var(--universal-padding)/2) var(--universal-padding);
border-radius: 1em; }
/*
Definitions for progress elements and spinners.
*/
/* Progress module CSS variable definitions */
:root {
--progress-back-color: #3cb4e6;
--progress-fore-color: #555; }
progress {
display: block;
vertical-align: baseline;
-webkit-appearance: none;
-moz-appearance: none;
appearance: none;
height: 0.75rem;
width: calc(100% - 2 * var(--universal-margin));
margin: var(--universal-margin);
border: 0;
border-radius: calc(2 * var(--universal-border-radius));
background: var(--progress-back-color);
color: var(--progress-fore-color); }
progress::-webkit-progress-value {
background: var(--progress-fore-color);
border-top-left-radius: calc(2 * var(--universal-border-radius));
border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
progress::-webkit-progress-bar {
background: var(--progress-back-color); }
progress::-moz-progress-bar {
background: var(--progress-fore-color);
border-top-left-radius: calc(2 * var(--universal-border-radius));
border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
progress[value="1000"]::-webkit-progress-value {
border-radius: calc(2 * var(--universal-border-radius)); }
progress[value="1000"]::-moz-progress-bar {
border-radius: calc(2 * var(--universal-border-radius)); }
progress.inline {
display: inline-block;
vertical-align: middle;
width: 60%; }
:root {
--spinner-back-color: #ddd;
--spinner-fore-color: #555; }
@keyframes spinner-donut-anim {
0% {
transform: rotate(0deg); }
100% {
transform: rotate(360deg); } }
.spinner {
display: inline-block;
margin: var(--universal-margin);
border: 0.25rem solid var(--spinner-back-color);
border-left: 0.25rem solid var(--spinner-fore-color);
border-radius: 50%;
width: 1.25rem;
height: 1.25rem;
animation: spinner-donut-anim 1.2s linear infinite; }
/*
Custom elements for progress bars and spinners.
*/
progress.primary {
--progress-fore-color: #1976d2; }
progress.secondary {
--progress-fore-color: #d32f2f; }
progress.tertiary {
--progress-fore-color: #308732; }
.spinner.primary {
--spinner-fore-color: #1976d2; }
.spinner.secondary {
--spinner-fore-color: #d32f2f; }
.spinner.tertiary {
--spinner-fore-color: #308732; }
/*
Definitions for icons - powered by Feather (https://feathericons.com/).
*/
span[class^='icon-'] {
display: inline-block;
height: 1em;
width: 1em;
vertical-align: -0.125em;
background-size: contain;
margin: 0 calc(var(--universal-margin) / 4); }
span[class^='icon-'].secondary {
-webkit-filter: invert(25%);
filter: invert(25%); }
span[class^='icon-'].inverse {
-webkit-filter: invert(100%);
filter: invert(100%); }
span.icon-alert {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-bookmark {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-calendar {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-credit {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-edit {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
span.icon-link {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-help {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-home {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
span.icon-info {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-lock {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-mail {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
span.icon-location {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
span.icon-phone {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-rss {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
span.icon-search {
background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-settings {
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/**
******************************************************************************
* @file lis2dw12_reg.c
* @author Sensors Software Solution Team
* @brief LIS2DW12 driver file
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
#include "lis2dw12_reg.h"
/**
* @defgroup LIS2DW12
* @brief This file provides a set of functions needed to drive the
* lis2dw12 enhanced inertial module.
* @{
*
*/
/**
* @defgroup LIS2DW12_Interfaces_Functions
* @brief This section provide a set of functions used to read and
* write a generic register of the device.
* MANDATORY: return 0 -> no Error.
* @{
*
*/
/**
* @brief Read generic device register
*
* @param ctx read / write interface definitions(ptr)
* @param reg register to read
* @param data pointer to buffer that store the data read(ptr)
* @param len number of consecutive register to read
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t __weak lis2dw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
uint8_t *data,
uint16_t len)
{
int32_t ret;
if (ctx == NULL)
{
return -1;
}
ret = ctx->read_reg(ctx->handle, reg, data, len);
return ret;
}
/**
* @brief Write generic device register
*
* @param ctx read / write interface definitions(ptr)
* @param reg register to write
* @param data pointer to data to write in register reg(ptr)
* @param len number of consecutive register to write
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t __weak lis2dw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
uint8_t *data,
uint16_t len)
{
int32_t ret;
if (ctx == NULL)
{
return -1;
}
ret = ctx->write_reg(ctx->handle, reg, data, len);
return ret;
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
*
*/
float_t lis2dw12_from_fs2_to_mg(int16_t lsb)
{
return ((float_t)lsb) * 0.061f;
}
float_t lis2dw12_from_fs4_to_mg(int16_t lsb)
{
return ((float_t)lsb) * 0.122f;
}
float_t lis2dw12_from_fs8_to_mg(int16_t lsb)
{
return ((float_t)lsb) * 0.244f;
}
float_t lis2dw12_from_fs16_to_mg(int16_t lsb)
{
return ((float_t)lsb) * 0.488f;
}
float_t lis2dw12_from_fs2_lp1_to_mg(int16_t lsb)
{
return ((float_t)lsb) * 0.061f;
}
float_t lis2dw12_from_fs4_lp1_to_mg(int16_t lsb)
{
return ((float_t)lsb) * 0.122f;
}
float_t lis2dw12_from_fs8_lp1_to_mg(int16_t lsb)
{
return ((float_t)lsb) * 0.244f;
}
float_t lis2dw12_from_fs16_lp1_to_mg(int16_t lsb)
{
return ((float_t)lsb) * 0.488f;
}
float_t lis2dw12_from_lsb_to_celsius(int16_t lsb)
{
return (((float_t)lsb / 256.0f) + 25.0f);
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Data_Generation
* @brief This section groups all the functions concerning
* data generation
* @{
*
*/
/**
* @brief Select accelerometer operating modes.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of mode / lp_mode in reg CTRL1
* and low_noise in reg CTRL6
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_power_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_mode_t val)
{
lis2dw12_ctrl1_t ctrl1;
lis2dw12_ctrl6_t ctrl6;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
if (ret == 0)
{
ctrl1.mode = ((uint8_t) val & 0x0CU) >> 2;
ctrl1.lp_mode = (uint8_t) val & 0x03U ;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
}
if (ret == 0)
{
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
}
if (ret == 0)
{
ctrl6.low_noise = ((uint8_t) val & 0x10U) >> 4;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
}
return ret;
}
/**
* @brief Select accelerometer operating modes.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of mode / lp_mode in reg CTRL1
* and low_noise in reg CTRL6
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_power_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_mode_t *val)
{
lis2dw12_ctrl1_t ctrl1;
lis2dw12_ctrl6_t ctrl6;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
if (ret == 0)
{
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) +
ctrl1.lp_mode))
{
case LIS2DW12_HIGH_PERFORMANCE:
*val = LIS2DW12_HIGH_PERFORMANCE;
break;
case LIS2DW12_CONT_LOW_PWR_4:
*val = LIS2DW12_CONT_LOW_PWR_4;
break;
case LIS2DW12_CONT_LOW_PWR_3:
*val = LIS2DW12_CONT_LOW_PWR_3;
break;
case LIS2DW12_CONT_LOW_PWR_2:
*val = LIS2DW12_CONT_LOW_PWR_2;
break;
case LIS2DW12_CONT_LOW_PWR_12bit:
*val = LIS2DW12_CONT_LOW_PWR_12bit;
break;
case LIS2DW12_SINGLE_LOW_PWR_4:
*val = LIS2DW12_SINGLE_LOW_PWR_4;
break;
case LIS2DW12_SINGLE_LOW_PWR_3:
*val = LIS2DW12_SINGLE_LOW_PWR_3;
break;
case LIS2DW12_SINGLE_LOW_PWR_2:
*val = LIS2DW12_SINGLE_LOW_PWR_2;
break;
case LIS2DW12_SINGLE_LOW_PWR_12bit:
*val = LIS2DW12_SINGLE_LOW_PWR_12bit;
break;
case LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE:
*val = LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE;
break;
case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4:
*val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4;
break;
case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3:
*val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3;
break;
case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2:
*val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2;
break;
case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit:
*val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit;
break;
case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4:
*val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4;
break;
case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3:
*val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3;
break;
case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2:
*val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2;
break;
case LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit:
*val = LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit;
break;
default:
*val = LIS2DW12_HIGH_PERFORMANCE;
break;
}
}
return ret;
}
/**
* @brief Accelerometer data rate selection.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of odr in reg CTRL1
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_data_rate_set(const stmdev_ctx_t *ctx, lis2dw12_odr_t val)
{
lis2dw12_ctrl1_t ctrl1;
lis2dw12_ctrl3_t ctrl3;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
if (ret == 0)
{
ctrl1.odr = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
}
if (ret == 0)
{
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
}
if (ret == 0)
{
ctrl3.slp_mode = ((uint8_t) val & 0x30U) >> 4;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
}
return ret;
}
/**
* @brief Accelerometer data rate selection.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of odr in reg CTRL1
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_data_rate_get(const stmdev_ctx_t *ctx, lis2dw12_odr_t *val)
{
lis2dw12_ctrl1_t ctrl1;
lis2dw12_ctrl3_t ctrl3;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
if (ret == 0)
{
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
switch ((ctrl3.slp_mode << 4) + ctrl1.odr)
{
case LIS2DW12_XL_ODR_OFF:
*val = LIS2DW12_XL_ODR_OFF;
break;
case LIS2DW12_XL_ODR_1Hz6_LP_ONLY:
*val = LIS2DW12_XL_ODR_1Hz6_LP_ONLY;
break;
case LIS2DW12_XL_ODR_12Hz5:
*val = LIS2DW12_XL_ODR_12Hz5;
break;
case LIS2DW12_XL_ODR_25Hz:
*val = LIS2DW12_XL_ODR_25Hz;
break;
case LIS2DW12_XL_ODR_50Hz:
*val = LIS2DW12_XL_ODR_50Hz;
break;
case LIS2DW12_XL_ODR_100Hz:
*val = LIS2DW12_XL_ODR_100Hz;
break;
case LIS2DW12_XL_ODR_200Hz:
*val = LIS2DW12_XL_ODR_200Hz;
break;
case LIS2DW12_XL_ODR_400Hz:
*val = LIS2DW12_XL_ODR_400Hz;
break;
case LIS2DW12_XL_ODR_800Hz:
*val = LIS2DW12_XL_ODR_800Hz;
break;
case LIS2DW12_XL_ODR_1k6Hz:
*val = LIS2DW12_XL_ODR_1k6Hz;
break;
case LIS2DW12_XL_SET_SW_TRIG:
*val = LIS2DW12_XL_SET_SW_TRIG;
break;
case LIS2DW12_XL_SET_PIN_TRIG:
*val = LIS2DW12_XL_SET_PIN_TRIG;
break;
default:
*val = LIS2DW12_XL_ODR_OFF;
break;
}
}
return ret;
}
/**
* @brief Block data update.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of bdu in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.bdu = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Block data update.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of bdu in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_block_data_update_get(const stmdev_ctx_t *ctx,
uint8_t *val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
*val = reg.bdu;
return ret;
}
/**
* @brief Accelerometer full-scale selection.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of fs in reg CTRL6
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_full_scale_set(const stmdev_ctx_t *ctx, lis2dw12_fs_t val)
{
lis2dw12_ctrl6_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.fs = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Accelerometer full-scale selection.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of fs in reg CTRL6
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_full_scale_get(const stmdev_ctx_t *ctx, lis2dw12_fs_t *val)
{
lis2dw12_ctrl6_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &reg, 1);
switch (reg.fs)
{
case LIS2DW12_2g:
*val = LIS2DW12_2g;
break;
case LIS2DW12_4g:
*val = LIS2DW12_4g;
break;
case LIS2DW12_8g:
*val = LIS2DW12_8g;
break;
case LIS2DW12_16g:
*val = LIS2DW12_16g;
break;
default:
*val = LIS2DW12_2g;
break;
}
return ret;
}
/**
* @brief The STATUS_REG register of the device.[get]
*
* @param ctx read / write interface definitions
* @param val union of registers from STATUS to
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_status_reg_get(const stmdev_ctx_t *ctx,
lis2dw12_status_t *val)
{
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t *) val, 1);
return ret;
}
/**
* @brief Accelerometer new data available.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of drdy in reg STATUS
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_status_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t *) &reg, 1);
*val = reg.drdy;
return ret;
}
/**
* @brief Read all the interrupt/status flag of the device.[get]
*
* @param ctx read / write interface definitions
* @param val registers STATUS_DUP, WAKE_UP_SRC,
* TAP_SRC, SIXD_SRC, ALL_INT_SRC
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_all_sources_get(const stmdev_ctx_t *ctx,
lis2dw12_all_sources_t *val)
{
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS_DUP, (uint8_t *) val, 5);
return ret;
}
/**
* @brief Accelerometer X-axis user offset correction expressed in two's
* complement, weight depends on bit USR_OFF_W. The value must be
* in the range [-127 127].[set]
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = lis2dw12_write_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1);
return ret;
}
/**
* @brief Accelerometer X-axis user offset correction expressed in two's
* complement, weight depends on bit USR_OFF_W. The value must be
* in the range [-127 127].[get]
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1);
return ret;
}
/**
* @brief Accelerometer Y-axis user offset correction expressed in two's
* complement, weight depends on bit USR_OFF_W. The value must be
* in the range [-127 127].[set]
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = lis2dw12_write_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1);
return ret;
}
/**
* @brief Accelerometer Y-axis user offset correction expressed in two's
* complement, weight depends on bit USR_OFF_W. The value must be
* in the range [-127 127].[get]
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1);
return ret;
}
/**
* @brief Accelerometer Z-axis user offset correction expressed in two's
* complement, weight depends on bit USR_OFF_W. The value must be
* in the range [-127 127].[set]
*
* @param ctx read / write interface definitions
* @param buff buffer that contains data to write
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = lis2dw12_write_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1);
return ret;
}
/**
* @brief Accelerometer Z-axis user offset correction expressed in two's
* complement, weight depends on bit USR_OFF_W. The value must be
* in the range [-127 127].[get]
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1);
return ret;
}
/**
* @brief Weight of XL user offset bits of registers X_OFS_USR,
* Y_OFS_USR, Z_OFS_USR.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_w in
* reg CTRL_REG7
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_offset_weight_set(const stmdev_ctx_t *ctx,
lis2dw12_usr_off_w_t val)
{
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.usr_off_w = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Weight of XL user offset bits of registers X_OFS_USR,
* Y_OFS_USR, Z_OFS_USR.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of usr_off_w in reg CTRL_REG7
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_offset_weight_get(const stmdev_ctx_t *ctx,
lis2dw12_usr_off_w_t *val)
{
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
switch (reg.usr_off_w)
{
case LIS2DW12_LSb_977ug:
*val = LIS2DW12_LSb_977ug;
break;
case LIS2DW12_LSb_15mg6:
*val = LIS2DW12_LSb_15mg6;
break;
default:
*val = LIS2DW12_LSb_977ug;
break;
}
return ret;
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Data_Output
* @brief This section groups all the data output functions.
* @{
*
*/
/**
* @brief Temperature data output register (r). L and H registers
* together express a 16-bit word in two's complement.[get]
*
* @param ctx read / write interface definitions
* @param val buffer that stores data read
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[2];
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_T_L, buff, 2);
*val = (int16_t)buff[1];
*val = (*val * 256) + (int16_t)buff[0];
return ret;
}
/**
* @brief Linear acceleration output register. The value is expressed as
* a 16-bit word in two's complement.[get]
*
* @param ctx read / write interface definitions
* @param val buffer that stores data read
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[6];
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_X_L, buff, 6);
val[0] = (int16_t)buff[1];
val[0] = (val[0] * 256) + (int16_t)buff[0];
val[1] = (int16_t)buff[3];
val[1] = (val[1] * 256) + (int16_t)buff[2];
val[2] = (int16_t)buff[5];
val[2] = (val[2] * 256) + (int16_t)buff[4];
return ret;
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Common
* @brief This section groups common useful functions.
* @{
*
*/
/**
* @brief Device Who am I.[get]
*
* @param ctx read / write interface definitions
* @param buff buffer that stores data read
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
{
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WHO_AM_I, buff, 1);
return ret;
}
/**
* @brief Register address automatically incremented during multiple byte
* access with a serial interface.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of if_add_inc in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.if_add_inc = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Register address automatically incremented during multiple
* byte access with a serial interface.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of if_add_inc in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
*val = reg.if_add_inc;
return ret;
}
/**
* @brief Software reset. Restore the default values in user registers.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of soft_reset in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.soft_reset = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Software reset. Restore the default values in user registers.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of soft_reset in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
*val = reg.soft_reset;
return ret;
}
/**
* @brief Reboot memory content. Reload the calibration parameters.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of boot in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.boot = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Reboot memory content. Reload the calibration parameters.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of boot in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
*val = reg.boot;
return ret;
}
/**
* @brief Sensor self-test enable.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of st in reg CTRL3
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_self_test_set(const stmdev_ctx_t *ctx, lis2dw12_st_t val)
{
lis2dw12_ctrl3_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.st = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Sensor self-test enable.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of st in reg CTRL3
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_self_test_get(const stmdev_ctx_t *ctx, lis2dw12_st_t *val)
{
lis2dw12_ctrl3_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &reg, 1);
switch (reg.st)
{
case LIS2DW12_XL_ST_DISABLE:
*val = LIS2DW12_XL_ST_DISABLE;
break;
case LIS2DW12_XL_ST_POSITIVE:
*val = LIS2DW12_XL_ST_POSITIVE;
break;
case LIS2DW12_XL_ST_NEGATIVE:
*val = LIS2DW12_XL_ST_NEGATIVE;
break;
default:
*val = LIS2DW12_XL_ST_DISABLE;
break;
}
return ret;
}
/**
* @brief Data-ready pulsed / letched mode.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of drdy_pulsed in reg CTRL_REG7
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_data_ready_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_drdy_pulsed_t val)
{
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.drdy_pulsed = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Data-ready pulsed / letched mode.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of drdy_pulsed in reg CTRL_REG7
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_data_ready_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_drdy_pulsed_t *val)
{
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
switch (reg.drdy_pulsed)
{
case LIS2DW12_DRDY_LATCHED:
*val = LIS2DW12_DRDY_LATCHED;
break;
case LIS2DW12_DRDY_PULSED:
*val = LIS2DW12_DRDY_PULSED;
break;
default:
*val = LIS2DW12_DRDY_LATCHED;
break;
}
return ret;
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Filters
* @brief This section group all the functions concerning the filters
* configuration.
* @{
*
*/
/**
* @brief Accelerometer filtering path for outputs.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of fds in reg CTRL6
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_filter_path_set(const stmdev_ctx_t *ctx,
lis2dw12_fds_t val)
{
lis2dw12_ctrl6_t ctrl6;
lis2dw12_ctrl_reg7_t ctrl_reg7;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
if (ret == 0)
{
ctrl6.fds = ((uint8_t) val & 0x10U) >> 4;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
}
if (ret == 0)
{
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,
(uint8_t *) &ctrl_reg7, 1);
}
if (ret == 0)
{
ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,
(uint8_t *) &ctrl_reg7, 1);
}
return ret;
}
/**
* @brief Accelerometer filtering path for outputs.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of fds in reg CTRL6
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_filter_path_get(const stmdev_ctx_t *ctx,
lis2dw12_fds_t *val)
{
lis2dw12_ctrl6_t ctrl6;
lis2dw12_ctrl_reg7_t ctrl_reg7;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
if (ret == 0)
{
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,
(uint8_t *) &ctrl_reg7, 1);
switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out)
{
case LIS2DW12_LPF_ON_OUT:
*val = LIS2DW12_LPF_ON_OUT;
break;
case LIS2DW12_USER_OFFSET_ON_OUT:
*val = LIS2DW12_USER_OFFSET_ON_OUT;
break;
case LIS2DW12_HIGH_PASS_ON_OUT:
*val = LIS2DW12_HIGH_PASS_ON_OUT;
break;
default:
*val = LIS2DW12_LPF_ON_OUT;
break;
}
}
return ret;
}
/**
* @brief Accelerometer cutoff filter frequency. Valid for low and high
* pass filter.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of bw_filt in reg CTRL6
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_filter_bandwidth_set(const stmdev_ctx_t *ctx,
lis2dw12_bw_filt_t val)
{
lis2dw12_ctrl6_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.bw_filt = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Accelerometer cutoff filter frequency. Valid for low and
* high pass filter.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of bw_filt in reg CTRL6
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_filter_bandwidth_get(const stmdev_ctx_t *ctx,
lis2dw12_bw_filt_t *val)
{
lis2dw12_ctrl6_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &reg, 1);
switch (reg.bw_filt)
{
case LIS2DW12_ODR_DIV_2:
*val = LIS2DW12_ODR_DIV_2;
break;
case LIS2DW12_ODR_DIV_4:
*val = LIS2DW12_ODR_DIV_4;
break;
case LIS2DW12_ODR_DIV_10:
*val = LIS2DW12_ODR_DIV_10;
break;
case LIS2DW12_ODR_DIV_20:
*val = LIS2DW12_ODR_DIV_20;
break;
default:
*val = LIS2DW12_ODR_DIV_2;
break;
}
return ret;
}
/**
* @brief Enable HP filter reference mode.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of hp_ref_mode in reg CTRL_REG7
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.hp_ref_mode = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Enable HP filter reference mode.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of hp_ref_mode in reg CTRL_REG7
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
*val = reg.hp_ref_mode;
return ret;
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Serial_Interface
* @brief This section groups all the functions concerning main serial
* interface management (not auxiliary)
* @{
*
*/
/**
* @brief SPI Serial Interface Mode selection.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of sim in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dw12_sim_t val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.sim = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief SPI Serial Interface Mode selection.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of sim in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dw12_sim_t *val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
switch (reg.sim)
{
case LIS2DW12_SPI_4_WIRE:
*val = LIS2DW12_SPI_4_WIRE;
break;
case LIS2DW12_SPI_3_WIRE:
*val = LIS2DW12_SPI_3_WIRE;
break;
default:
*val = LIS2DW12_SPI_4_WIRE;
break;
}
return ret;
}
/**
* @brief Disable / Enable I2C interface.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of i2c_disable in
* reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_i2c_interface_set(const stmdev_ctx_t *ctx,
lis2dw12_i2c_disable_t val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.i2c_disable = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Disable / Enable I2C interface.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of i2c_disable in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_i2c_interface_get(const stmdev_ctx_t *ctx,
lis2dw12_i2c_disable_t *val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
switch (reg.i2c_disable)
{
case LIS2DW12_I2C_ENABLE:
*val = LIS2DW12_I2C_ENABLE;
break;
case LIS2DW12_I2C_DISABLE:
*val = LIS2DW12_I2C_DISABLE;
break;
default:
*val = LIS2DW12_I2C_ENABLE;
break;
}
return ret;
}
/**
* @brief Disconnect CS pull-up.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of cs_pu_disc in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_cs_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_cs_pu_disc_t val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.cs_pu_disc = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Disconnect CS pull-up.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of cs_pu_disc in reg CTRL2
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_cs_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_cs_pu_disc_t *val)
{
lis2dw12_ctrl2_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) &reg, 1);
switch (reg.cs_pu_disc)
{
case LIS2DW12_PULL_UP_CONNECT:
*val = LIS2DW12_PULL_UP_CONNECT;
break;
case LIS2DW12_PULL_UP_DISCONNECT:
*val = LIS2DW12_PULL_UP_DISCONNECT;
break;
default:
*val = LIS2DW12_PULL_UP_CONNECT;
break;
}
return ret;
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Interrupt_Pins
* @brief This section groups all the functions that manage interrupt pins
* @{
*
*/
/**
* @brief Interrupt active-high/low.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of h_lactive in reg CTRL3
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_pin_polarity_set(const stmdev_ctx_t *ctx,
lis2dw12_h_lactive_t val)
{
lis2dw12_ctrl3_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.h_lactive = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Interrupt active-high/low.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of h_lactive in reg CTRL3
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_pin_polarity_get(const stmdev_ctx_t *ctx,
lis2dw12_h_lactive_t *val)
{
lis2dw12_ctrl3_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &reg, 1);
switch (reg.h_lactive)
{
case LIS2DW12_ACTIVE_HIGH:
*val = LIS2DW12_ACTIVE_HIGH;
break;
case LIS2DW12_ACTIVE_LOW:
*val = LIS2DW12_ACTIVE_LOW;
break;
default:
*val = LIS2DW12_ACTIVE_HIGH;
break;
}
return ret;
}
/**
* @brief Latched/pulsed interrupt.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of lir in reg CTRL3
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_int_notification_set(const stmdev_ctx_t *ctx,
lis2dw12_lir_t val)
{
lis2dw12_ctrl3_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.lir = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Latched/pulsed interrupt.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of lir in reg CTRL3
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_int_notification_get(const stmdev_ctx_t *ctx,
lis2dw12_lir_t *val)
{
lis2dw12_ctrl3_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &reg, 1);
switch (reg.lir)
{
case LIS2DW12_INT_PULSED:
*val = LIS2DW12_INT_PULSED;
break;
case LIS2DW12_INT_LATCHED:
*val = LIS2DW12_INT_LATCHED;
break;
default:
*val = LIS2DW12_INT_PULSED;
break;
}
return ret;
}
/**
* @brief Push-pull/open drain selection on interrupt pads.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of pp_od in reg CTRL3
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_pin_mode_set(const stmdev_ctx_t *ctx, lis2dw12_pp_od_t val)
{
lis2dw12_ctrl3_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.pp_od = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Push-pull/open drain selection on interrupt pads.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of pp_od in reg CTRL3
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_pin_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_pp_od_t *val)
{
lis2dw12_ctrl3_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &reg, 1);
switch (reg.pp_od)
{
case LIS2DW12_PUSH_PULL:
*val = LIS2DW12_PUSH_PULL;
break;
case LIS2DW12_OPEN_DRAIN:
*val = LIS2DW12_OPEN_DRAIN;
break;
default:
*val = LIS2DW12_PUSH_PULL;
break;
}
return ret;
}
/**
* @brief Select the signal that need to route on int1 pad.[set]
*
* @param ctx read / write interface definitions
* @param val register CTRL4_INT1_PAD_CTRL.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_pin_int1_route_set(const stmdev_ctx_t *ctx,
lis2dw12_ctrl4_int1_pad_ctrl_t *val)
{
lis2dw12_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl;
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
(uint8_t *)&ctrl5_int2_pad_ctrl, 1);
if (ret == 0)
{
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
}
if (ret == 0)
{
if ((val->int1_tap |
val->int1_ff |
val->int1_wu |
val->int1_single_tap |
val->int1_6d |
ctrl5_int2_pad_ctrl.int2_sleep_state |
ctrl5_int2_pad_ctrl.int2_sleep_chg) != PROPERTY_DISABLE)
{
reg.interrupts_enable = PROPERTY_ENABLE;
}
else
{
reg.interrupts_enable = PROPERTY_DISABLE;
}
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
(uint8_t *) val, 1);
}
if (ret == 0)
{
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Select the signal that need to route on int1 pad.[get]
*
* @param ctx read / write interface definitions
* @param val register CTRL4_INT1_PAD_CTRL.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_pin_int1_route_get(const stmdev_ctx_t *ctx,
lis2dw12_ctrl4_int1_pad_ctrl_t *val)
{
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
(uint8_t *) val, 1);
return ret;
}
/**
* @brief Select the signal that need to route on int2 pad.[set]
*
* @param ctx read / write interface definitions
* @param val register CTRL5_INT2_PAD_CTRL.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_pin_int2_route_set(const stmdev_ctx_t *ctx,
lis2dw12_ctrl5_int2_pad_ctrl_t *val)
{
lis2dw12_ctrl4_int1_pad_ctrl_t ctrl4_int1_pad_ctrl;
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
(uint8_t *) &ctrl4_int1_pad_ctrl, 1);
if (ret == 0)
{
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
}
if (ret == 0)
{
if ((ctrl4_int1_pad_ctrl.int1_tap |
ctrl4_int1_pad_ctrl.int1_ff |
ctrl4_int1_pad_ctrl.int1_wu |
ctrl4_int1_pad_ctrl.int1_single_tap |
ctrl4_int1_pad_ctrl.int1_6d |
val->int2_sleep_state | val->int2_sleep_chg) != PROPERTY_DISABLE)
{
reg.interrupts_enable = PROPERTY_ENABLE;
}
else
{
reg.interrupts_enable = PROPERTY_DISABLE;
}
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
(uint8_t *) val, 1);
}
if (ret == 0)
{
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Select the signal that need to route on int2 pad.[get]
*
* @param ctx read / write interface definitions
* @param val register CTRL5_INT2_PAD_CTRL
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_pin_int2_route_get(const stmdev_ctx_t *ctx,
lis2dw12_ctrl5_int2_pad_ctrl_t *val)
{
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
(uint8_t *) val, 1);
return ret;
}
/**
* @brief All interrupt signals become available on INT1 pin.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of int2_on_int1 in reg CTRL_REG7
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.int2_on_int1 = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief All interrupt signals become available on INT1 pin.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of int2_on_int1 in reg CTRL_REG7
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
*val = reg.int2_on_int1;
return ret;
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Wake_Up_Event
* @brief This section groups all the functions that manage the Wake
* Up event generation.
* @{
*
*/
/**
* @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of wk_ths in reg WAKE_UP_THS
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_wake_up_ths_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.wk_ths = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of wk_ths in reg WAKE_UP_THS
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_wake_up_ths_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) &reg, 1);
*val = reg.wk_ths;
return ret;
}
/**
* @brief Wake up duration event.1LSb = 1 / ODR.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of wake_dur in reg WAKE_UP_DUR
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_wake_up_dur_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.wake_dur = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Wake up duration event.1LSb = 1 / ODR.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of wake_dur in reg WAKE_UP_DUR
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_wake_up_dur_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &reg, 1);
*val = reg.wake_dur;
return ret;
}
/**
* @brief Data sent to wake-up interrupt function.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of usr_off_on_wu in reg CTRL_REG7
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_wkup_feed_data_set(const stmdev_ctx_t *ctx,
lis2dw12_usr_off_on_wu_t val)
{
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.usr_off_on_wu = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Data sent to wake-up interrupt function.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of usr_off_on_wu in reg CTRL_REG7
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_wkup_feed_data_get(const stmdev_ctx_t *ctx,
lis2dw12_usr_off_on_wu_t *val)
{
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
switch (reg.usr_off_on_wu)
{
case LIS2DW12_HP_FEED:
*val = LIS2DW12_HP_FEED;
break;
case LIS2DW12_USER_OFFSET_FEED:
*val = LIS2DW12_USER_OFFSET_FEED;
break;
default:
*val = LIS2DW12_HP_FEED;
break;
}
return ret;
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Activity/Inactivity_Detection
* @brief This section groups all the functions concerning
* activity/inactivity detection.
* @{
*
*/
/**
* @brief Config activity / inactivity or
* stationary / motion detection.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_on / stationary in
* reg WAKE_UP_THS / WAKE_UP_DUR
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_act_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_sleep_on_t val)
{
lis2dw12_wake_up_ths_t wake_up_ths;
lis2dw12_wake_up_dur_t wake_up_dur;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,
(uint8_t *) &wake_up_ths, 1);
if (ret == 0)
{
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,
(uint8_t *) &wake_up_dur, 1);
}
if (ret == 0)
{
wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS,
(uint8_t *) &wake_up_ths, 1);
}
if (ret == 0)
{
wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,
(uint8_t *) &wake_up_dur, 1);
}
return ret;
}
/**
* @brief Config activity / inactivity or
* stationary / motion detection. [get]
*
* @param ctx read / write interface definitions
* @param val Get the values of sleep_on in reg WAKE_UP_THS
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_act_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_sleep_on_t *val)
{
lis2dw12_wake_up_ths_t wake_up_ths;
lis2dw12_wake_up_dur_t wake_up_dur;;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,
(uint8_t *) &wake_up_ths, 1);
if (ret == 0)
{
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,
(uint8_t *) &wake_up_dur, 1);
switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on)
{
case LIS2DW12_NO_DETECTION:
*val = LIS2DW12_NO_DETECTION;
break;
case LIS2DW12_DETECT_ACT_INACT:
*val = LIS2DW12_DETECT_ACT_INACT;
break;
case LIS2DW12_DETECT_STAT_MOTION:
*val = LIS2DW12_DETECT_STAT_MOTION;
break;
default:
*val = LIS2DW12_NO_DETECTION;
break;
}
}
return ret;
}
/**
* @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_dur in reg WAKE_UP_DUR
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_wake_up_dur_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.sleep_dur = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get]
*
* @param ctx read / write interface definitions
* @param val change the values of sleep_dur in reg WAKE_UP_DUR
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_wake_up_dur_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &reg, 1);
*val = reg.sleep_dur;
return ret;
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Tap_Generator
* @brief This section groups all the functions that manage the tap
* and double tap event generation.
* @{
*
*/
/**
* @brief Threshold for tap recognition.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_thsx in reg TAP_THS_X
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_tap_ths_x_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.tap_thsx = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Threshold for tap recognition.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_thsx in reg TAP_THS_X
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_tap_ths_x_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) &reg, 1);
*val = reg.tap_thsx;
return ret;
}
/**
* @brief Threshold for tap recognition.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_thsy in reg TAP_THS_Y
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_tap_ths_y_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.tap_thsy = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Threshold for tap recognition.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_thsy in reg TAP_THS_Y
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_tap_ths_y_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) &reg, 1);
*val = reg.tap_thsy;
return ret;
}
/**
* @brief Selection of axis priority for TAP detection.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_prior in reg TAP_THS_Y
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_axis_priority_set(const stmdev_ctx_t *ctx,
lis2dw12_tap_prior_t val)
{
lis2dw12_tap_ths_y_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.tap_prior = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Selection of axis priority for TAP detection.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of tap_prior in reg TAP_THS_Y
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_axis_priority_get(const stmdev_ctx_t *ctx,
lis2dw12_tap_prior_t *val)
{
lis2dw12_tap_ths_y_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) &reg, 1);
switch (reg.tap_prior)
{
case LIS2DW12_XYZ:
*val = LIS2DW12_XYZ;
break;
case LIS2DW12_YXZ:
*val = LIS2DW12_YXZ;
break;
case LIS2DW12_XZY:
*val = LIS2DW12_XZY;
break;
case LIS2DW12_ZYX:
*val = LIS2DW12_ZYX;
break;
case LIS2DW12_YZX:
*val = LIS2DW12_YZX;
break;
case LIS2DW12_ZXY:
*val = LIS2DW12_ZXY;
break;
default:
*val = LIS2DW12_XYZ;
break;
}
return ret;
}
/**
* @brief Threshold for tap recognition.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_thsz in reg TAP_THS_Z
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.tap_thsz = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Threshold for tap recognition.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_thsz in reg TAP_THS_Z
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) &reg, 1);
*val = reg.tap_thsz;
return ret;
}
/**
* @brief Enable Z direction in tap recognition.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_z_en in reg TAP_THS_Z
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
uint8_t val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.tap_z_en = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Enable Z direction in tap recognition.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_z_en in reg TAP_THS_Z
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
uint8_t *val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) &reg, 1);
*val = reg.tap_z_en;
return ret;
}
/**
* @brief Enable Y direction in tap recognition.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_y_en in reg TAP_THS_Z
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
uint8_t val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.tap_y_en = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Enable Y direction in tap recognition.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_y_en in reg TAP_THS_Z
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
uint8_t *val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) &reg, 1);
*val = reg.tap_y_en;
return ret;
}
/**
* @brief Enable X direction in tap recognition.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_x_en in reg TAP_THS_Z
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
uint8_t val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.tap_x_en = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Enable X direction in tap recognition.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of tap_x_en in reg TAP_THS_Z
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
uint8_t *val)
{
lis2dw12_tap_ths_z_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) &reg, 1);
*val = reg.tap_x_en;
return ret;
}
/**
* @brief Maximum duration is the maximum time of an overthreshold signal
* detection to be recognized as a tap event. The default value
* of these bits is 00b which corresponds to 4*ODR_XL time.
* If the SHOCK[1:0] bits are set to a different value, 1LSB
* corresponds to 8*ODR_XL time.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of shock in reg INT_DUR
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_int_dur_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.shock = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Maximum duration is the maximum time of an overthreshold signal
* detection to be recognized as a tap event. The default value
* of these bits is 00b which corresponds to 4*ODR_XL time.
* If the SHOCK[1:0] bits are set to a different value, 1LSB
* corresponds to 8*ODR_XL time.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of shock in reg INT_DUR
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_int_dur_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) &reg, 1);
*val = reg.shock;
return ret;
}
/**
* @brief Quiet time is the time after the first detected tap in which
* there must not be any overthreshold event.
* The default value of these bits is 00b which corresponds
* to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
* value, 1LSB corresponds to 4*ODR_XL time.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of quiet in reg INT_DUR
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_int_dur_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.quiet = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Quiet time is the time after the first detected tap in which
* there must not be any overthreshold event.
* The default value of these bits is 00b which corresponds
* to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
* value, 1LSB corresponds to 4*ODR_XL time.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of quiet in reg INT_DUR
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_int_dur_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) &reg, 1);
*val = reg.quiet;
return ret;
}
/**
* @brief When double tap recognition is enabled, this register expresses
* the maximum time between two consecutive detected taps to
* determine a double tap event.
* The default value of these bits is 0000b which corresponds
* to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
* value, 1LSB corresponds to 32*ODR_XL time.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of latency in reg INT_DUR
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_int_dur_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.latency = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief When double tap recognition is enabled, this register expresses
* the maximum time between two consecutive detected taps to
* determine a double tap event.
* The default value of these bits is 0000b which corresponds
* to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
* value, 1LSB corresponds to 32*ODR_XL time.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of latency in reg INT_DUR
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_int_dur_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) &reg, 1);
*val = reg.latency;
return ret;
}
/**
* @brief Single/double-tap event enable.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of single_double_tap in reg WAKE_UP_THS
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_single_double_tap_t val)
{
lis2dw12_wake_up_ths_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.single_double_tap = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Single/double-tap event enable.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of single_double_tap in reg WAKE_UP_THS
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_single_double_tap_t *val)
{
lis2dw12_wake_up_ths_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) &reg, 1);
switch (reg.single_double_tap)
{
case LIS2DW12_ONLY_SINGLE:
*val = LIS2DW12_ONLY_SINGLE;
break;
case LIS2DW12_BOTH_SINGLE_DOUBLE:
*val = LIS2DW12_BOTH_SINGLE_DOUBLE;
break;
default:
*val = LIS2DW12_ONLY_SINGLE;
break;
}
return ret;
}
/**
* @brief Read the tap / double tap source register.[get]
*
* @param ctx read / write interface definitions
* @param lis2dw12_tap_src: union of registers from TAP_SRC to
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_tap_src_get(const stmdev_ctx_t *ctx,
lis2dw12_tap_src_t *val)
{
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_SRC, (uint8_t *) val, 1);
return ret;
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Six_Position_Detection(6D/4D)
* @brief This section groups all the functions concerning six
* position detection (6D).
* @{
*
*/
/**
* @brief Threshold for 4D/6D function.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of 6d_ths in reg TAP_THS_X
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_tap_ths_x_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg._6d_ths = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Threshold for 4D/6D function.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of 6d_ths in reg TAP_THS_X
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_tap_ths_x_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) &reg, 1);
*val = reg._6d_ths;
return ret;
}
/**
* @brief 4D orientation detection enable.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of 4d_en in reg TAP_THS_X
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_tap_ths_x_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg._4d_en = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief 4D orientation detection enable.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of 4d_en in reg TAP_THS_X
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_tap_ths_x_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) &reg, 1);
*val = reg._4d_en;
return ret;
}
/**
* @brief Read the 6D tap source register.[get]
*
* @param ctx read / write interface definitions
* @param val union of registers from SIXD_SRC
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_6d_src_get(const stmdev_ctx_t *ctx,
lis2dw12_sixd_src_t *val)
{
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_SIXD_SRC, (uint8_t *) val, 1);
return ret;
}
/**
* @brief Data sent to 6D interrupt function.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of lpass_on6d in reg CTRL_REG7
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_6d_feed_data_set(const stmdev_ctx_t *ctx,
lis2dw12_lpass_on6d_t val)
{
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.lpass_on6d = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Data sent to 6D interrupt function.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of lpass_on6d in reg CTRL_REG7
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_6d_feed_data_get(const stmdev_ctx_t *ctx,
lis2dw12_lpass_on6d_t *val)
{
lis2dw12_ctrl_reg7_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) &reg, 1);
switch (reg.lpass_on6d)
{
case LIS2DW12_ODR_DIV_2_FEED:
*val = LIS2DW12_ODR_DIV_2_FEED;
break;
case LIS2DW12_LPF2_FEED:
*val = LIS2DW12_LPF2_FEED;
break;
default:
*val = LIS2DW12_ODR_DIV_2_FEED;
break;
}
return ret;
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Free_Fall
* @brief This section group all the functions concerning
* the free fall detection.
* @{
*
*/
/**
* @brief Free fall duration event(1LSb = 1 / ODR).[set]
*
* @param ctx read / write interface definitions
* @param val change the values of ff_dur in reg
* WAKE_UP_DUR /F REE_FALL
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_wake_up_dur_t wake_up_dur;
lis2dw12_free_fall_t free_fall;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,
(uint8_t *) &wake_up_dur, 1);
if (ret == 0)
{
ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,
(uint8_t *) &free_fall, 1);
}
if (ret == 0)
{
wake_up_dur.ff_dur = ((uint8_t) val & 0x20U) >> 5;
free_fall.ff_dur = (uint8_t) val & 0x1FU;
ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,
(uint8_t *) &wake_up_dur, 1);
}
if (ret == 0)
{
ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL,
(uint8_t *) &free_fall, 1);
}
return ret;
}
/**
* @brief Free fall duration event(1LSb = 1 / ODR).[get]
*
* @param ctx read / write interface definitions
* @param val change the values of ff_dur in
* reg WAKE_UP_DUR /F REE_FALL
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_wake_up_dur_t wake_up_dur;
lis2dw12_free_fall_t free_fall;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,
(uint8_t *) &wake_up_dur, 1);
if (ret == 0)
{
ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,
(uint8_t *) &free_fall, 1);
*val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
}
return ret;
}
/**
* @brief Free fall threshold setting.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of ff_ths in reg FREE_FALL
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_ff_threshold_set(const stmdev_ctx_t *ctx,
lis2dw12_ff_ths_t val)
{
lis2dw12_free_fall_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.ff_ths = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief Free fall threshold setting.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of ff_ths in reg FREE_FALL
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_ff_threshold_get(const stmdev_ctx_t *ctx,
lis2dw12_ff_ths_t *val)
{
lis2dw12_free_fall_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) &reg, 1);
switch (reg.ff_ths)
{
case LIS2DW12_FF_TSH_5LSb_FS2g:
*val = LIS2DW12_FF_TSH_5LSb_FS2g;
break;
case LIS2DW12_FF_TSH_7LSb_FS2g:
*val = LIS2DW12_FF_TSH_7LSb_FS2g;
break;
case LIS2DW12_FF_TSH_8LSb_FS2g:
*val = LIS2DW12_FF_TSH_8LSb_FS2g;
break;
case LIS2DW12_FF_TSH_10LSb_FS2g:
*val = LIS2DW12_FF_TSH_10LSb_FS2g;
break;
case LIS2DW12_FF_TSH_11LSb_FS2g:
*val = LIS2DW12_FF_TSH_11LSb_FS2g;
break;
case LIS2DW12_FF_TSH_13LSb_FS2g:
*val = LIS2DW12_FF_TSH_13LSb_FS2g;
break;
case LIS2DW12_FF_TSH_15LSb_FS2g:
*val = LIS2DW12_FF_TSH_15LSb_FS2g;
break;
case LIS2DW12_FF_TSH_16LSb_FS2g:
*val = LIS2DW12_FF_TSH_16LSb_FS2g;
break;
default:
*val = LIS2DW12_FF_TSH_5LSb_FS2g;
break;
}
return ret;
}
/**
* @}
*
*/
/**
* @defgroup LIS2DW12_Fifo
* @brief This section group all the functions concerning the fifo usage
* @{
*
*/
/**
* @brief FIFO watermark level selection.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of fth in reg FIFO_CTRL
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2dw12_fifo_ctrl_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.fth = val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief FIFO watermark level selection.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of fth in reg FIFO_CTRL
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_fifo_ctrl_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) &reg, 1);
*val = reg.fth;
return ret;
}
/**
* @brief FIFO mode selection.[set]
*
* @param ctx read / write interface definitions
* @param val change the values of fmode in reg FIFO_CTRL
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_fifo_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_fmode_t val)
{
lis2dw12_fifo_ctrl_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) &reg, 1);
if (ret == 0)
{
reg.fmode = (uint8_t) val;
ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) &reg, 1);
}
return ret;
}
/**
* @brief FIFO mode selection.[get]
*
* @param ctx read / write interface definitions
* @param val Get the values of fmode in reg FIFO_CTRL
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_fifo_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_fmode_t *val)
{
lis2dw12_fifo_ctrl_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) &reg, 1);
switch (reg.fmode)
{
case LIS2DW12_BYPASS_MODE:
*val = LIS2DW12_BYPASS_MODE;
break;
case LIS2DW12_FIFO_MODE:
*val = LIS2DW12_FIFO_MODE;
break;
case LIS2DW12_STREAM_TO_FIFO_MODE:
*val = LIS2DW12_STREAM_TO_FIFO_MODE;
break;
case LIS2DW12_BYPASS_TO_STREAM_MODE:
*val = LIS2DW12_BYPASS_TO_STREAM_MODE;
break;
case LIS2DW12_STREAM_MODE:
*val = LIS2DW12_STREAM_MODE;
break;
default:
*val = LIS2DW12_BYPASS_MODE;
break;
}
return ret;
}
/**
* @brief Number of unread samples stored in FIFO.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of diff in reg FIFO_SAMPLES
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_fifo_samples_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) &reg, 1);
*val = reg.diff;
return ret;
}
/**
* @brief FIFO overrun status.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_ovr in reg FIFO_SAMPLES
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_fifo_samples_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) &reg, 1);
*val = reg.fifo_ovr;
return ret;
}
/**
* @brief FIFO threshold status flag.[get]
*
* @param ctx read / write interface definitions
* @param val change the values of fifo_fth in reg FIFO_SAMPLES
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2dw12_fifo_samples_t reg;
int32_t ret;
ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) &reg, 1);
*val = reg.fifo_fth;
return ret;
}
/**
* @}
*
*/
/**
* @}
*
*/
/**
******************************************************************************
* @file lis2dw12_reg.h
* @author Sensors Software Solution Team
* @brief This file contains all the functions prototypes for the
* lis2dw12_reg.c driver.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LIS2DW12_REGS_H
#define LIS2DW12_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
#include <stddef.h>
#include <math.h>
/** @addtogroup LIS2DW12
* @{
*
*/
/** @defgroup Endianness definitions
* @{
*
*/
#ifndef DRV_BYTE_ORDER
#ifndef __BYTE_ORDER__
#define DRV_LITTLE_ENDIAN 1234
#define DRV_BIG_ENDIAN 4321
/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
* by uncommenting the define which fits your platform endianness
*/
//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
#else /* defined __BYTE_ORDER__ */
#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
#define DRV_BYTE_ORDER __BYTE_ORDER__
#endif /* __BYTE_ORDER__*/
#endif /* DRV_BYTE_ORDER */
/**
* @}
*
*/
/** @defgroup STMicroelectronics sensors common types
* @{
*
*/
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
uint8_t bit3 : 1;
uint8_t bit4 : 1;
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t bit7 : 1;
uint8_t bit6 : 1;
uint8_t bit5 : 1;
uint8_t bit4 : 1;
uint8_t bit3 : 1;
uint8_t bit2 : 1;
uint8_t bit1 : 1;
uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
#define PROPERTY_ENABLE (1U)
/** @addtogroup Interfaces_Functions
* @brief This section provide a set of functions used to read and
* write a generic register of the device.
* MANDATORY: return 0 -> no Error.
* @{
*
*/
typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
typedef void (*stmdev_mdelay_ptr)(uint32_t millisec);
typedef struct
{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
/** Component optional fields **/
stmdev_mdelay_ptr mdelay;
/** Customizable optional pointer **/
void *handle;
/** private data **/
void *priv_data;
} stmdev_ctx_t;
/**
* @}
*
*/
#endif /* MEMS_SHARED_TYPES */
#ifndef MEMS_UCF_SHARED_TYPES
#define MEMS_UCF_SHARED_TYPES
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
* You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
* @{
*
*/
typedef struct
{
uint8_t address;
uint8_t data;
} ucf_line_t;
/**
* @}
*
*/
#endif /* MEMS_UCF_SHARED_TYPES */
/**
* @}
*
*/
/** @defgroup LIS2DW12_Infos
* @{
*
*/
/** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/
#define LIS2DW12_I2C_ADD_L 0x31U
#define LIS2DW12_I2C_ADD_H 0x33U
/** Device Identification (Who am I) **/
#define LIS2DW12_ID 0x44U
/**
* @}
*
*/
#define LIS2DW12_OUT_T_L 0x0DU
#define LIS2DW12_OUT_T_H 0x0EU
#define LIS2DW12_WHO_AM_I 0x0FU
#define LIS2DW12_CTRL1 0x20U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lp_mode : 2;
uint8_t mode : 2;
uint8_t odr : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t odr : 4;
uint8_t mode : 2;
uint8_t lp_mode : 2;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_ctrl1_t;
#define LIS2DW12_CTRL2 0x21U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sim : 1;
uint8_t i2c_disable : 1;
uint8_t if_add_inc : 1;
uint8_t bdu : 1;
uint8_t cs_pu_disc : 1;
uint8_t not_used_01 : 1;
uint8_t soft_reset : 1;
uint8_t boot : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t boot : 1;
uint8_t soft_reset : 1;
uint8_t not_used_01 : 1;
uint8_t cs_pu_disc : 1;
uint8_t bdu : 1;
uint8_t if_add_inc : 1;
uint8_t i2c_disable : 1;
uint8_t sim : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_ctrl2_t;
#define LIS2DW12_CTRL3 0x22U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */
uint8_t not_used_01 : 1;
uint8_t h_lactive : 1;
uint8_t lir : 1;
uint8_t pp_od : 1;
uint8_t st : 2;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t st : 2;
uint8_t pp_od : 1;
uint8_t lir : 1;
uint8_t h_lactive : 1;
uint8_t not_used_01 : 1;
uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */
#endif /* DRV_BYTE_ORDER */
} lis2dw12_ctrl3_t;
#define LIS2DW12_CTRL4_INT1_PAD_CTRL 0x23U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy : 1;
uint8_t int1_fth : 1;
uint8_t int1_diff5 : 1;
uint8_t int1_tap : 1;
uint8_t int1_ff : 1;
uint8_t int1_wu : 1;
uint8_t int1_single_tap : 1;
uint8_t int1_6d : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t int1_6d : 1;
uint8_t int1_single_tap : 1;
uint8_t int1_wu : 1;
uint8_t int1_ff : 1;
uint8_t int1_tap : 1;
uint8_t int1_diff5 : 1;
uint8_t int1_fth : 1;
uint8_t int1_drdy : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_ctrl4_int1_pad_ctrl_t;
#define LIS2DW12_CTRL5_INT2_PAD_CTRL 0x24U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy : 1;
uint8_t int2_fth : 1;
uint8_t int2_diff5 : 1;
uint8_t int2_ovr : 1;
uint8_t int2_drdy_t : 1;
uint8_t int2_boot : 1;
uint8_t int2_sleep_chg : 1;
uint8_t int2_sleep_state : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t int2_sleep_state : 1;
uint8_t int2_sleep_chg : 1;
uint8_t int2_boot : 1;
uint8_t int2_drdy_t : 1;
uint8_t int2_ovr : 1;
uint8_t int2_diff5 : 1;
uint8_t int2_fth : 1;
uint8_t int2_drdy : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_ctrl5_int2_pad_ctrl_t;
#define LIS2DW12_CTRL6 0x25U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used_01 : 2;
uint8_t low_noise : 1;
uint8_t fds : 1;
uint8_t fs : 2;
uint8_t bw_filt : 2;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t bw_filt : 2;
uint8_t fs : 2;
uint8_t fds : 1;
uint8_t low_noise : 1;
uint8_t not_used_01 : 2;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_ctrl6_t;
#define LIS2DW12_OUT_T 0x26U
#define LIS2DW12_STATUS 0x27U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
uint8_t _6d_ia : 1;
uint8_t single_tap : 1;
uint8_t double_tap : 1;
uint8_t sleep_state : 1;
uint8_t wu_ia : 1;
uint8_t fifo_ths : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fifo_ths : 1;
uint8_t wu_ia : 1;
uint8_t sleep_state : 1;
uint8_t double_tap : 1;
uint8_t single_tap : 1;
uint8_t _6d_ia : 1;
uint8_t ff_ia : 1;
uint8_t drdy : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_status_t;
#define LIS2DW12_OUT_X_L 0x28U
#define LIS2DW12_OUT_X_H 0x29U
#define LIS2DW12_OUT_Y_L 0x2AU
#define LIS2DW12_OUT_Y_H 0x2BU
#define LIS2DW12_OUT_Z_L 0x2CU
#define LIS2DW12_OUT_Z_H 0x2DU
#define LIS2DW12_FIFO_CTRL 0x2EU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fth : 5;
uint8_t fmode : 3;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fmode : 3;
uint8_t fth : 5;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_fifo_ctrl_t;
#define LIS2DW12_FIFO_SAMPLES 0x2FU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff : 6;
uint8_t fifo_ovr : 1;
uint8_t fifo_fth : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fifo_fth : 1;
uint8_t fifo_ovr : 1;
uint8_t diff : 6;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_fifo_samples_t;
#define LIS2DW12_TAP_THS_X 0x30U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_thsx : 5;
uint8_t _6d_ths : 2;
uint8_t _4d_en : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t _4d_en : 1;
uint8_t _6d_ths : 2;
uint8_t tap_thsx : 5;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_tap_ths_x_t;
#define LIS2DW12_TAP_THS_Y 0x31U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_thsy : 5;
uint8_t tap_prior : 3;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t tap_prior : 3;
uint8_t tap_thsy : 5;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_tap_ths_y_t;
#define LIS2DW12_TAP_THS_Z 0x32U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t tap_thsz : 5;
uint8_t tap_z_en : 1;
uint8_t tap_y_en : 1;
uint8_t tap_x_en : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t tap_x_en : 1;
uint8_t tap_y_en : 1;
uint8_t tap_z_en : 1;
uint8_t tap_thsz : 5;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_tap_ths_z_t;
#define LIS2DW12_INT_DUR 0x33U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t shock : 2;
uint8_t quiet : 2;
uint8_t latency : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t latency : 4;
uint8_t quiet : 2;
uint8_t shock : 2;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_int_dur_t;
#define LIS2DW12_WAKE_UP_THS 0x34U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wk_ths : 6;
uint8_t sleep_on : 1;
uint8_t single_double_tap : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t single_double_tap : 1;
uint8_t sleep_on : 1;
uint8_t wk_ths : 6;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_wake_up_ths_t;
#define LIS2DW12_WAKE_UP_DUR 0x35U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sleep_dur : 4;
uint8_t stationary : 1;
uint8_t wake_dur : 2;
uint8_t ff_dur : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ff_dur : 1;
uint8_t wake_dur : 2;
uint8_t stationary : 1;
uint8_t sleep_dur : 4;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_wake_up_dur_t;
#define LIS2DW12_FREE_FALL 0x36U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ths : 3;
uint8_t ff_dur : 5;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ff_dur : 5;
uint8_t ff_ths : 3;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_free_fall_t;
#define LIS2DW12_STATUS_DUP 0x37U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t drdy : 1;
uint8_t ff_ia : 1;
uint8_t _6d_ia : 1;
uint8_t single_tap : 1;
uint8_t double_tap : 1;
uint8_t sleep_state_ia : 1;
uint8_t drdy_t : 1;
uint8_t ovr : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ovr : 1;
uint8_t drdy_t : 1;
uint8_t sleep_state_ia : 1;
uint8_t double_tap : 1;
uint8_t single_tap : 1;
uint8_t _6d_ia : 1;
uint8_t ff_ia : 1;
uint8_t drdy : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_status_dup_t;
#define LIS2DW12_WAKE_UP_SRC 0x38U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
uint8_t wu_ia : 1;
uint8_t sleep_state_ia : 1;
uint8_t ff_ia : 1;
uint8_t not_used_01 : 2;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 2;
uint8_t ff_ia : 1;
uint8_t sleep_state_ia : 1;
uint8_t wu_ia : 1;
uint8_t x_wu : 1;
uint8_t y_wu : 1;
uint8_t z_wu : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_wake_up_src_t;
#define LIS2DW12_TAP_SRC 0x39U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t z_tap : 1;
uint8_t y_tap : 1;
uint8_t x_tap : 1;
uint8_t tap_sign : 1;
uint8_t double_tap : 1;
uint8_t single_tap : 1;
uint8_t tap_ia : 1;
uint8_t not_used_01 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 1;
uint8_t tap_ia : 1;
uint8_t single_tap : 1;
uint8_t double_tap : 1;
uint8_t tap_sign : 1;
uint8_t x_tap : 1;
uint8_t y_tap : 1;
uint8_t z_tap : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_tap_src_t;
#define LIS2DW12_SIXD_SRC 0x3AU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t yl : 1;
uint8_t yh : 1;
uint8_t zl : 1;
uint8_t zh : 1;
uint8_t _6d_ia : 1;
uint8_t not_used_01 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 1;
uint8_t _6d_ia : 1;
uint8_t zh : 1;
uint8_t zl : 1;
uint8_t yh : 1;
uint8_t xh : 1;
uint8_t yl : 1;
uint8_t xh : 1;
uint8_t xl : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_sixd_src_t;
#define LIS2DW12_ALL_INT_SRC 0x3BU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
uint8_t single_tap : 1;
uint8_t double_tap : 1;
uint8_t _6d_ia : 1;
uint8_t sleep_change_ia : 1;
uint8_t not_used_01 : 2;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used_01 : 2;
uint8_t sleep_change_ia : 1;
uint8_t _6d_ia : 1;
uint8_t double_tap : 1;
uint8_t single_tap : 1;
uint8_t wu_ia : 1;
uint8_t ff_ia : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_all_int_src_t;
#define LIS2DW12_X_OFS_USR 0x3CU
#define LIS2DW12_Y_OFS_USR 0x3DU
#define LIS2DW12_Z_OFS_USR 0x3EU
#define LIS2DW12_CTRL_REG7 0x3FU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lpass_on6d : 1;
uint8_t hp_ref_mode : 1;
uint8_t usr_off_w : 1;
uint8_t usr_off_on_wu : 1;
uint8_t usr_off_on_out : 1;
uint8_t interrupts_enable : 1;
uint8_t int2_on_int1 : 1;
uint8_t drdy_pulsed : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t drdy_pulsed : 1;
uint8_t int2_on_int1 : 1;
uint8_t interrupts_enable : 1;
uint8_t usr_off_on_out : 1;
uint8_t usr_off_on_wu : 1;
uint8_t usr_off_w : 1;
uint8_t hp_ref_mode : 1;
uint8_t lpass_on6d : 1;
#endif /* DRV_BYTE_ORDER */
} lis2dw12_ctrl_reg7_t;
/**
* @defgroup LIS2DW12_Register_Union
* @brief This union group all the registers having a bit-field
* description.
* This union is useful but it's not needed by the driver.
*
* REMOVING this union you are compliant with:
* MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
*
* @{
*
*/
typedef union
{
lis2dw12_ctrl1_t ctrl1;
lis2dw12_ctrl2_t ctrl2;
lis2dw12_ctrl3_t ctrl3;
lis2dw12_ctrl4_int1_pad_ctrl_t ctrl4_int1_pad_ctrl;
lis2dw12_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl;
lis2dw12_ctrl6_t ctrl6;
lis2dw12_status_t status;
lis2dw12_fifo_ctrl_t fifo_ctrl;
lis2dw12_fifo_samples_t fifo_samples;
lis2dw12_tap_ths_x_t tap_ths_x;
lis2dw12_tap_ths_y_t tap_ths_y;
lis2dw12_tap_ths_z_t tap_ths_z;
lis2dw12_int_dur_t int_dur;
lis2dw12_wake_up_ths_t wake_up_ths;
lis2dw12_wake_up_dur_t wake_up_dur;
lis2dw12_free_fall_t free_fall;
lis2dw12_status_dup_t status_dup;
lis2dw12_wake_up_src_t wake_up_src;
lis2dw12_tap_src_t tap_src;
lis2dw12_sixd_src_t sixd_src;
lis2dw12_all_int_src_t all_int_src;
lis2dw12_ctrl_reg7_t ctrl_reg7;
bitwise_t bitwise;
uint8_t byte;
} lis2dw12_reg_t;
/**
* @}
*
*/
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
/*
* These are the basic platform dependent I/O routines to read
* and write device registers connected on a standard bus.
* The driver keeps offering a default implementation based on function
* pointers to read/write routines for backward compatibility.
* The __weak directive allows the final application to overwrite
* them with a custom implementation.
*/
int32_t lis2dw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
uint8_t *data,
uint16_t len);
int32_t lis2dw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
uint8_t *data,
uint16_t len);
float_t lis2dw12_from_fs2_to_mg(int16_t lsb);
float_t lis2dw12_from_fs4_to_mg(int16_t lsb);
float_t lis2dw12_from_fs8_to_mg(int16_t lsb);
float_t lis2dw12_from_fs16_to_mg(int16_t lsb);
float_t lis2dw12_from_fs2_lp1_to_mg(int16_t lsb);
float_t lis2dw12_from_fs4_lp1_to_mg(int16_t lsb);
float_t lis2dw12_from_fs8_lp1_to_mg(int16_t lsb);
float_t lis2dw12_from_fs16_lp1_to_mg(int16_t lsb);
float_t lis2dw12_from_lsb_to_celsius(int16_t lsb);
typedef enum
{
LIS2DW12_HIGH_PERFORMANCE = 0x04,
LIS2DW12_CONT_LOW_PWR_4 = 0x03,
LIS2DW12_CONT_LOW_PWR_3 = 0x02,
LIS2DW12_CONT_LOW_PWR_2 = 0x01,
LIS2DW12_CONT_LOW_PWR_12bit = 0x00,
LIS2DW12_SINGLE_LOW_PWR_4 = 0x0B,
LIS2DW12_SINGLE_LOW_PWR_3 = 0x0A,
LIS2DW12_SINGLE_LOW_PWR_2 = 0x09,
LIS2DW12_SINGLE_LOW_PWR_12bit = 0x08,
LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE = 0x14,
LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4 = 0x13,
LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3 = 0x12,
LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2 = 0x11,
LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit = 0x10,
LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4 = 0x1B,
LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3 = 0x1A,
LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2 = 0x19,
LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit = 0x18,
} lis2dw12_mode_t;
int32_t lis2dw12_power_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_mode_t val);
int32_t lis2dw12_power_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_mode_t *val);
typedef enum
{
LIS2DW12_XL_ODR_OFF = 0x00,
LIS2DW12_XL_ODR_1Hz6_LP_ONLY = 0x01,
LIS2DW12_XL_ODR_12Hz5 = 0x02,
LIS2DW12_XL_ODR_25Hz = 0x03,
LIS2DW12_XL_ODR_50Hz = 0x04,
LIS2DW12_XL_ODR_100Hz = 0x05,
LIS2DW12_XL_ODR_200Hz = 0x06,
LIS2DW12_XL_ODR_400Hz = 0x07,
LIS2DW12_XL_ODR_800Hz = 0x08,
LIS2DW12_XL_ODR_1k6Hz = 0x09,
LIS2DW12_XL_SET_SW_TRIG = 0x32, /* Use this only in SINGLE mode */
LIS2DW12_XL_SET_PIN_TRIG = 0x12, /* Use this only in SINGLE mode */
} lis2dw12_odr_t;
int32_t lis2dw12_data_rate_set(const stmdev_ctx_t *ctx, lis2dw12_odr_t val);
int32_t lis2dw12_data_rate_get(const stmdev_ctx_t *ctx,
lis2dw12_odr_t *val);
int32_t lis2dw12_block_data_update_set(const stmdev_ctx_t *ctx,
uint8_t val);
int32_t lis2dw12_block_data_update_get(const stmdev_ctx_t *ctx,
uint8_t *val);
typedef enum
{
LIS2DW12_2g = 0,
LIS2DW12_4g = 1,
LIS2DW12_8g = 2,
LIS2DW12_16g = 3,
} lis2dw12_fs_t;
int32_t lis2dw12_full_scale_set(const stmdev_ctx_t *ctx, lis2dw12_fs_t val);
int32_t lis2dw12_full_scale_get(const stmdev_ctx_t *ctx,
lis2dw12_fs_t *val);
int32_t lis2dw12_status_reg_get(const stmdev_ctx_t *ctx,
lis2dw12_status_t *val);
int32_t lis2dw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val);
typedef struct
{
lis2dw12_status_dup_t status_dup;
lis2dw12_wake_up_src_t wake_up_src;
lis2dw12_tap_src_t tap_src;
lis2dw12_sixd_src_t sixd_src;
lis2dw12_all_int_src_t all_int_src;
} lis2dw12_all_sources_t;
int32_t lis2dw12_all_sources_get(const stmdev_ctx_t *ctx,
lis2dw12_all_sources_t *val);
int32_t lis2dw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis2dw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis2dw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis2dw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis2dw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis2dw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff);
typedef enum
{
LIS2DW12_LSb_977ug = 0,
LIS2DW12_LSb_15mg6 = 1,
} lis2dw12_usr_off_w_t;
int32_t lis2dw12_offset_weight_set(const stmdev_ctx_t *ctx,
lis2dw12_usr_off_w_t val);
int32_t lis2dw12_offset_weight_get(const stmdev_ctx_t *ctx,
lis2dw12_usr_off_w_t *val);
int32_t lis2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val);
int32_t lis2dw12_acceleration_raw_get(const stmdev_ctx_t *ctx,
int16_t *val);
int32_t lis2dw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff);
int32_t lis2dw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val);
typedef enum
{
LIS2DW12_XL_ST_DISABLE = 0,
LIS2DW12_XL_ST_POSITIVE = 1,
LIS2DW12_XL_ST_NEGATIVE = 2,
} lis2dw12_st_t;
int32_t lis2dw12_self_test_set(const stmdev_ctx_t *ctx, lis2dw12_st_t val);
int32_t lis2dw12_self_test_get(const stmdev_ctx_t *ctx, lis2dw12_st_t *val);
typedef enum
{
LIS2DW12_DRDY_LATCHED = 0,
LIS2DW12_DRDY_PULSED = 1,
} lis2dw12_drdy_pulsed_t;
int32_t lis2dw12_data_ready_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_drdy_pulsed_t val);
int32_t lis2dw12_data_ready_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_drdy_pulsed_t *val);
typedef enum
{
LIS2DW12_LPF_ON_OUT = 0x00,
LIS2DW12_USER_OFFSET_ON_OUT = 0x01,
LIS2DW12_HIGH_PASS_ON_OUT = 0x10,
} lis2dw12_fds_t;
int32_t lis2dw12_filter_path_set(const stmdev_ctx_t *ctx,
lis2dw12_fds_t val);
int32_t lis2dw12_filter_path_get(const stmdev_ctx_t *ctx,
lis2dw12_fds_t *val);
typedef enum
{
LIS2DW12_ODR_DIV_2 = 0,
LIS2DW12_ODR_DIV_4 = 1,
LIS2DW12_ODR_DIV_10 = 2,
LIS2DW12_ODR_DIV_20 = 3,
} lis2dw12_bw_filt_t;
int32_t lis2dw12_filter_bandwidth_set(const stmdev_ctx_t *ctx,
lis2dw12_bw_filt_t val);
int32_t lis2dw12_filter_bandwidth_get(const stmdev_ctx_t *ctx,
lis2dw12_bw_filt_t *val);
int32_t lis2dw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val);
typedef enum
{
LIS2DW12_SPI_4_WIRE = 0,
LIS2DW12_SPI_3_WIRE = 1,
} lis2dw12_sim_t;
int32_t lis2dw12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dw12_sim_t val);
int32_t lis2dw12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dw12_sim_t *val);
typedef enum
{
LIS2DW12_I2C_ENABLE = 0,
LIS2DW12_I2C_DISABLE = 1,
} lis2dw12_i2c_disable_t;
int32_t lis2dw12_i2c_interface_set(const stmdev_ctx_t *ctx,
lis2dw12_i2c_disable_t val);
int32_t lis2dw12_i2c_interface_get(const stmdev_ctx_t *ctx,
lis2dw12_i2c_disable_t *val);
typedef enum
{
LIS2DW12_PULL_UP_CONNECT = 0,
LIS2DW12_PULL_UP_DISCONNECT = 1,
} lis2dw12_cs_pu_disc_t;
int32_t lis2dw12_cs_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_cs_pu_disc_t val);
int32_t lis2dw12_cs_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_cs_pu_disc_t *val);
typedef enum
{
LIS2DW12_ACTIVE_HIGH = 0,
LIS2DW12_ACTIVE_LOW = 1,
} lis2dw12_h_lactive_t;
int32_t lis2dw12_pin_polarity_set(const stmdev_ctx_t *ctx,
lis2dw12_h_lactive_t val);
int32_t lis2dw12_pin_polarity_get(const stmdev_ctx_t *ctx,
lis2dw12_h_lactive_t *val);
typedef enum
{
LIS2DW12_INT_PULSED = 0,
LIS2DW12_INT_LATCHED = 1,
} lis2dw12_lir_t;
int32_t lis2dw12_int_notification_set(const stmdev_ctx_t *ctx,
lis2dw12_lir_t val);
int32_t lis2dw12_int_notification_get(const stmdev_ctx_t *ctx,
lis2dw12_lir_t *val);
typedef enum
{
LIS2DW12_PUSH_PULL = 0,
LIS2DW12_OPEN_DRAIN = 1,
} lis2dw12_pp_od_t;
int32_t lis2dw12_pin_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_pp_od_t val);
int32_t lis2dw12_pin_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_pp_od_t *val);
int32_t lis2dw12_pin_int1_route_set(const stmdev_ctx_t *ctx,
lis2dw12_ctrl4_int1_pad_ctrl_t *val);
int32_t lis2dw12_pin_int1_route_get(const stmdev_ctx_t *ctx,
lis2dw12_ctrl4_int1_pad_ctrl_t *val);
int32_t lis2dw12_pin_int2_route_set(const stmdev_ctx_t *ctx,
lis2dw12_ctrl5_int2_pad_ctrl_t *val);
int32_t lis2dw12_pin_int2_route_get(const stmdev_ctx_t *ctx,
lis2dw12_ctrl5_int2_pad_ctrl_t *val);
int32_t lis2dw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val);
typedef enum
{
LIS2DW12_HP_FEED = 0,
LIS2DW12_USER_OFFSET_FEED = 1,
} lis2dw12_usr_off_on_wu_t;
int32_t lis2dw12_wkup_feed_data_set(const stmdev_ctx_t *ctx,
lis2dw12_usr_off_on_wu_t val);
int32_t lis2dw12_wkup_feed_data_get(const stmdev_ctx_t *ctx,
lis2dw12_usr_off_on_wu_t *val);
typedef enum
{
LIS2DW12_NO_DETECTION = 0,
LIS2DW12_DETECT_ACT_INACT = 1,
LIS2DW12_DETECT_STAT_MOTION = 3,
} lis2dw12_sleep_on_t;
int32_t lis2dw12_act_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_sleep_on_t val);
int32_t lis2dw12_act_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_sleep_on_t *val);
int32_t lis2dw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val);
typedef enum
{
LIS2DW12_XYZ = 0,
LIS2DW12_YXZ = 1,
LIS2DW12_XZY = 2,
LIS2DW12_ZYX = 3,
LIS2DW12_YZX = 5,
LIS2DW12_ZXY = 6,
} lis2dw12_tap_prior_t;
int32_t lis2dw12_tap_axis_priority_set(const stmdev_ctx_t *ctx,
lis2dw12_tap_prior_t val);
int32_t lis2dw12_tap_axis_priority_get(const stmdev_ctx_t *ctx,
lis2dw12_tap_prior_t *val);
int32_t lis2dw12_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
uint8_t val);
int32_t lis2dw12_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
uint8_t *val);
int32_t lis2dw12_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
uint8_t val);
int32_t lis2dw12_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
uint8_t *val);
int32_t lis2dw12_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
uint8_t val);
int32_t lis2dw12_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
uint8_t *val);
int32_t lis2dw12_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val);
typedef enum
{
LIS2DW12_ONLY_SINGLE = 0,
LIS2DW12_BOTH_SINGLE_DOUBLE = 1,
} lis2dw12_single_double_tap_t;
int32_t lis2dw12_tap_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_single_double_tap_t val);
int32_t lis2dw12_tap_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_single_double_tap_t *val);
int32_t lis2dw12_tap_src_get(const stmdev_ctx_t *ctx,
lis2dw12_tap_src_t *val);
int32_t lis2dw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_6d_src_get(const stmdev_ctx_t *ctx,
lis2dw12_sixd_src_t *val);
typedef enum
{
LIS2DW12_ODR_DIV_2_FEED = 0,
LIS2DW12_LPF2_FEED = 1,
} lis2dw12_lpass_on6d_t;
int32_t lis2dw12_6d_feed_data_set(const stmdev_ctx_t *ctx,
lis2dw12_lpass_on6d_t val);
int32_t lis2dw12_6d_feed_data_get(const stmdev_ctx_t *ctx,
lis2dw12_lpass_on6d_t *val);
int32_t lis2dw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val);
typedef enum
{
LIS2DW12_FF_TSH_5LSb_FS2g = 0,
LIS2DW12_FF_TSH_7LSb_FS2g = 1,
LIS2DW12_FF_TSH_8LSb_FS2g = 2,
LIS2DW12_FF_TSH_10LSb_FS2g = 3,
LIS2DW12_FF_TSH_11LSb_FS2g = 4,
LIS2DW12_FF_TSH_13LSb_FS2g = 5,
LIS2DW12_FF_TSH_15LSb_FS2g = 6,
LIS2DW12_FF_TSH_16LSb_FS2g = 7,
} lis2dw12_ff_ths_t;
int32_t lis2dw12_ff_threshold_set(const stmdev_ctx_t *ctx,
lis2dw12_ff_ths_t val);
int32_t lis2dw12_ff_threshold_get(const stmdev_ctx_t *ctx,
lis2dw12_ff_ths_t *val);
int32_t lis2dw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val);
int32_t lis2dw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val);
typedef enum
{
LIS2DW12_BYPASS_MODE = 0,
LIS2DW12_FIFO_MODE = 1,
LIS2DW12_STREAM_TO_FIFO_MODE = 3,
LIS2DW12_BYPASS_TO_STREAM_MODE = 4,
LIS2DW12_STREAM_MODE = 6,
} lis2dw12_fmode_t;
int32_t lis2dw12_fifo_mode_set(const stmdev_ctx_t *ctx,
lis2dw12_fmode_t val);
int32_t lis2dw12_fifo_mode_get(const stmdev_ctx_t *ctx,
lis2dw12_fmode_t *val);
int32_t lis2dw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val);
int32_t lis2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val);
/**
* @}
*
*/
#ifdef __cplusplus
}
#endif
#endif /*LIS2DW12_REGS_H */
...@@ -12,7 +12,7 @@ dependencies: ...@@ -12,7 +12,7 @@ dependencies:
idf: idf:
source: source:
type: idf type: idf
version: 5.4.1 version: 5.5.0
direct_dependencies: direct_dependencies:
- espressif/led_strip - espressif/led_strip
manifest_hash: a9af7824fb34850fbe175d5384052634b3c00880abb2d3a7937e666d07603998 manifest_hash: a9af7824fb34850fbe175d5384052634b3c00880abb2d3a7937e666d07603998
......
Subproject commit f0326c61f95dbd6b69bd323fd5847a81476b7148
idf_component_register(SRCS "blink_example_main.c" idf_component_register(SRCS "blink_example_main.c" "lis2dw12.c"
INCLUDE_DIRS ".") INCLUDE_DIRS "."
REQUIRES "driver" "lis2dw12-pid" "esp_driver_i2c"
)
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include "esp_log.h" #include "esp_log.h"
#include "led_strip.h" #include "led_strip.h"
#include "sdkconfig.h" #include "sdkconfig.h"
#include "lis2dw12.h"
static const char *TAG = "example"; static const char *TAG = "example";
...@@ -76,12 +77,22 @@ static void blink_led(void) ...@@ -76,12 +77,22 @@ static void blink_led(void)
gpio_set_level(BLINK_GPIO, s_led_state); gpio_set_level(BLINK_GPIO, s_led_state);
} }
static void blink_led_g(void)
{
/* Set the GPIO level according to the state (LOW or HIGH)*/
gpio_set_level(9, s_led_state);
}
static void configure_led(void) static void configure_led(void)
{ {
ESP_LOGI(TAG, "Example configured to blink GPIO LED!"); ESP_LOGI(TAG, "Example configured to blink GPIO LED!");
gpio_reset_pin(BLINK_GPIO); gpio_reset_pin(BLINK_GPIO);
/* Set the GPIO as a push/pull output */ /* Set the GPIO as a push/pull output */
gpio_set_direction(BLINK_GPIO, GPIO_MODE_OUTPUT); gpio_set_direction(BLINK_GPIO, GPIO_MODE_OUTPUT);
gpio_reset_pin(9);
/* Set the GPIO as a push/pull output */
gpio_set_direction(9, GPIO_MODE_OUTPUT);
} }
#else #else
...@@ -93,12 +104,14 @@ void app_main(void) ...@@ -93,12 +104,14 @@ void app_main(void)
/* Configure the peripheral according to the LED type */ /* Configure the peripheral according to the LED type */
configure_led(); configure_led();
lis2dw12_init();
while (1) { while (1) {
ESP_LOGI(TAG, "Turning the LED %s!", s_led_state == true ? "ON" : "OFF"); ESP_LOGI(TAG, "Turning the LED %s!", s_led_state == true ? "ON" : "OFF");
blink_led(); blink_led();
blink_led_g();
/* Toggle the LED state */ /* Toggle the LED state */
s_led_state = !s_led_state; s_led_state = !s_led_state;
vTaskDelay(CONFIG_BLINK_PERIOD / portTICK_PERIOD_MS); vTaskDelay(1000 / portTICK_PERIOD_MS);
} }
} }
#include "lis2dw12.h"
#include "esp_err.h"
#include "driver/i2c_master.h"
#include "driver/gpio.h"
#include "esp_log.h"
#include "freertos/idf_additions.h"
#include "lis2dw12_reg.h"
#include "esp_sleep.h"
#include <string.h>
#define I2C_MASTER_SCL_IO 18 /*!< GPIO number used for I2C master clock */
#define I2C_MASTER_SDA_IO 19 /*!< GPIO number used for I2C master data */
#define I2C_MASTER_NUM 0 /*!< I2C master i2c port number, the number of i2c peripheral interfaces available will depend on the chip */
#define I2C_MASTER_FREQ_HZ 400000 /*!< I2C master clock frequency */
#define I2C_MASTER_TX_BUF_DISABLE 0 /*!< I2C master doesn't need buffer */
#define I2C_MASTER_RX_BUF_DISABLE 0 /*!< I2C master doesn't need buffer */
#define I2C_MASTER_TIMEOUT_MS 1000
#define SLAVE_ADDR 0x19
#define DEFAULT_WAKEUP_PIN 5
#define DEFAULT_WAKEUP_LEVEL ESP_GPIO_WAKEUP_GPIO_HIGH
#define TAG "LIS2DW12"
stmdev_ctx_t dev_ctx;
i2c_master_bus_handle_t s_bus_handle = NULL;
i2c_master_dev_handle_t s_dev_handle = NULL;
static void lis2dw12_wake_config(void);
/**
* @brief i2c master initialization
*/
static void i2c_master_init(i2c_master_bus_handle_t *bus_handle, i2c_master_dev_handle_t *dev_handle)
{
i2c_master_bus_config_t bus_config = {
.i2c_port = I2C_MASTER_NUM,
.sda_io_num = I2C_MASTER_SDA_IO,
.scl_io_num = I2C_MASTER_SCL_IO,
.clk_source = I2C_CLK_SRC_DEFAULT,
.glitch_ignore_cnt = 7,
.flags.enable_internal_pullup = true,
};
ESP_ERROR_CHECK(i2c_new_master_bus(&bus_config, bus_handle));
i2c_device_config_t dev_config = {
.dev_addr_length = I2C_ADDR_BIT_LEN_7,
.device_address = SLAVE_ADDR,
.scl_speed_hz = I2C_MASTER_FREQ_HZ,
};
ESP_ERROR_CHECK(i2c_master_bus_add_device(*bus_handle, &dev_config, dev_handle));
}
/**
* @brief Read a sequence of bytes from a lis2dw12 sensor registers
*/
static long int lis2dw12_register_read(void* dev_handle, uint8_t reg_addr, uint8_t *data, uint16_t len)
{
return i2c_master_transmit_receive((i2c_master_dev_handle_t)s_dev_handle, &reg_addr, 1, data, len, I2C_MASTER_TIMEOUT_MS / portTICK_PERIOD_MS);
}
/**
* @brief Write a byte to a lis2dw12 sensor register
*/
static long int lis2dw12_register_write_byte(void* dev_handle, uint8_t reg_addr, const unsigned char *data, short unsigned int len)
{
uint8_t write_buf[2] = {reg_addr, *data};
return i2c_master_transmit((i2c_master_dev_handle_t)s_dev_handle, write_buf, sizeof(write_buf), I2C_MASTER_TIMEOUT_MS / portTICK_PERIOD_MS);
}
static void i2c_master_delay_ms(uint32_t millisec)
{
vTaskDelay(millisec / portTICK_PERIOD_MS);
}
static void WakeupEnable(void)
{
const gpio_config_t config = {
.pin_bit_mask = BIT(DEFAULT_WAKEUP_PIN),
.mode = GPIO_MODE_INPUT,
};
ESP_ERROR_CHECK(gpio_config(&config));
ESP_ERROR_CHECK(esp_deep_sleep_enable_gpio_wakeup(BIT(DEFAULT_WAKEUP_PIN), DEFAULT_WAKEUP_LEVEL));
}
void lis2dw12_init()
{
static uint8_t whoamI, rst;
uint8_t tx_buffer[1000];
ESP_LOGI(TAG, "LIS2DW12 Init");
gpio_set_direction(I2C_MASTER_SCL_IO, GPIO_MODE_INPUT_OUTPUT_OD);
gpio_set_direction(I2C_MASTER_SDA_IO, GPIO_MODE_INPUT_OUTPUT_OD);
gpio_set_pull_mode(I2C_MASTER_SCL_IO, GPIO_PULLUP_ONLY);
gpio_set_pull_mode(I2C_MASTER_SDA_IO, GPIO_PULLUP_ONLY);
vTaskDelay(pdMS_TO_TICKS(50));
i2c_master_init(&s_bus_handle, &s_dev_handle);
ESP_LOGI(TAG, "LIS2DW12 Init 2");
vTaskDelay(pdMS_TO_TICKS(50));
dev_ctx.handle = &s_dev_handle;
dev_ctx.read_reg = lis2dw12_register_read;
dev_ctx.write_reg = lis2dw12_register_write_byte;
dev_ctx.mdelay = i2c_master_delay_ms;
ESP_LOGI(TAG, "LIS2DW12 Init 3");
while(1){
ESP_LOGI(TAG, "LIS2DW12 Init 4");
// lis2dw12_register_read(s_dev_handle, LIS2DW12_WHO_AM_I, &whoamI, 1);
lis2dw12_device_id_get(&dev_ctx, &whoamI);
if (whoamI != LIS2DW12_ID)
{
ESP_LOGE(TAG, "LIS2DW12 device ID not match (0x%02X)",whoamI);
}
else {
ESP_LOGI(TAG, "LIS2DW12 device ID: 0x%02X", whoamI);
break;
}
vTaskDelay(pdMS_TO_TICKS(50));
}
/* Restore default configuration */
lis2dw12_reset_set(&dev_ctx, PROPERTY_ENABLE);
do {
lis2dw12_reset_get(&dev_ctx, &rst);
} while (rst);
ESP_LOGI(TAG, "LIS2DW12 reset done");
ESP_LOGI(TAG, "LIS2DW12 Start Config Regiseter");
// WakeupEnable();
lis2dw12_wake_config();
ESP_LOGI(TAG, "LIS2DW12 Start Config Done");
while (1) {
lis2dw12_all_sources_t all_source;
/* Check Wake-Up events */
lis2dw12_all_sources_get(&dev_ctx, &all_source);
if (all_source.wake_up_src.wu_ia) {
snprintf((char *)tx_buffer, sizeof(tx_buffer), "Wake-Up event on ");
if (all_source.wake_up_src.x_wu) {
strcat((char *)tx_buffer, "X");
}
if (all_source.wake_up_src.y_wu) {
strcat((char *)tx_buffer, "Y");
}
if (all_source.wake_up_src.z_wu) {
strcat((char *)tx_buffer, "Z");
}
strcat((char *)tx_buffer, " direction\r\n");
ESP_LOGI(TAG, "%s", tx_buffer);
}
}
}
static void lis2dw12_wake_config(void)
{
lis2dw12_reg_t int_route;
lis2dw12_fs_t fs;
/* Set full scale */
lis2dw12_full_scale_set(&dev_ctx, LIS2DW12_16g);
lis2dw12_full_scale_get(&dev_ctx, &fs);
ESP_LOGI(TAG, "LIS2DW12 full scale: %d", fs);
/* Configure power mode */
lis2dw12_power_mode_set(&dev_ctx,
LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit);
/* Set Output Data Rate */
lis2dw12_data_rate_set(&dev_ctx, LIS2DW12_XL_ODR_200Hz);
/* Apply high-pass digital filter on Wake-Up function */
lis2dw12_filter_path_set(&dev_ctx, LIS2DW12_HIGH_PASS_ON_OUT);
/* Apply high-pass digital filter on Wake-Up function
* Duration time is set to zero so Wake-Up interrupt signal
* is generated for each X,Y,Z filtered data exceeding the
* configured threshold
*/
lis2dw12_wkup_dur_set(&dev_ctx, 0);
/* Set wake-up threshold
* Set Wake-Up threshold: 1 LSb corresponds to FS_XL/2^6
*/
lis2dw12_wkup_threshold_set(&dev_ctx, 1);
/* Enable interrupt generation on Wake-Up INT1 pin */
lis2dw12_pin_int1_route_get(&dev_ctx, &int_route.ctrl4_int1_pad_ctrl);
int_route.ctrl4_int1_pad_ctrl.int1_wu = PROPERTY_ENABLE;
lis2dw12_pin_int1_route_set(&dev_ctx, &int_route.ctrl4_int1_pad_ctrl);
}
\ No newline at end of file
#ifndef __LIS2DW12_H__
#define __LIS2DW12_H__
#include "stdio.h"
#include "stdlib.h"
void lis2dw12_init();
#endif
# #
# Automatically generated file. DO NOT EDIT. # Automatically generated file. DO NOT EDIT.
# Espressif IoT Development Framework (ESP-IDF) 5.4.1 Project Configuration # Espressif IoT Development Framework (ESP-IDF) 5.5.0 Project Configuration
# #
CONFIG_SOC_ADC_SUPPORTED=y CONFIG_SOC_ADC_SUPPORTED=y
CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y
CONFIG_SOC_UART_SUPPORTED=y CONFIG_SOC_UART_SUPPORTED=y
CONFIG_SOC_GDMA_SUPPORTED=y CONFIG_SOC_GDMA_SUPPORTED=y
CONFIG_SOC_UHCI_SUPPORTED=y
CONFIG_SOC_AHB_GDMA_SUPPORTED=y CONFIG_SOC_AHB_GDMA_SUPPORTED=y
CONFIG_SOC_GPTIMER_SUPPORTED=y CONFIG_SOC_GPTIMER_SUPPORTED=y
CONFIG_SOC_TWAI_SUPPORTED=y CONFIG_SOC_TWAI_SUPPORTED=y
...@@ -79,6 +80,7 @@ CONFIG_SOC_ADC_SHARED_POWER=y ...@@ -79,6 +80,7 @@ CONFIG_SOC_ADC_SHARED_POWER=y
CONFIG_SOC_APB_BACKUP_DMA=y CONFIG_SOC_APB_BACKUP_DMA=y
CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y
CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y
CONFIG_SOC_CACHE_FREEZE_SUPPORTED=y
CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE=0x4000 CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE=0x4000
CONFIG_SOC_CPU_CORES_NUM=1 CONFIG_SOC_CPU_CORES_NUM=1
CONFIG_SOC_CPU_INTR_NUM=32 CONFIG_SOC_CPU_INTR_NUM=32
...@@ -129,7 +131,10 @@ CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y ...@@ -129,7 +131,10 @@ CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y
CONFIG_SOC_I2S_SUPPORTS_PCM=y CONFIG_SOC_I2S_SUPPORTS_PCM=y
CONFIG_SOC_I2S_SUPPORTS_PDM=y CONFIG_SOC_I2S_SUPPORTS_PDM=y
CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y
CONFIG_SOC_I2S_SUPPORTS_PCM2PDM=y
CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y
CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2 CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2
CONFIG_SOC_I2S_PDM_MAX_RX_LINES=1
CONFIG_SOC_I2S_SUPPORTS_TDM=y CONFIG_SOC_I2S_SUPPORTS_TDM=y
CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y
CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y
...@@ -219,6 +224,7 @@ CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO=32 ...@@ -219,6 +224,7 @@ CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO=32
CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI=16 CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI=16
CONFIG_SOC_MWDT_SUPPORT_XTAL=y CONFIG_SOC_MWDT_SUPPORT_XTAL=y
CONFIG_SOC_TWAI_CONTROLLER_NUM=1 CONFIG_SOC_TWAI_CONTROLLER_NUM=1
CONFIG_SOC_TWAI_MASK_FILTER_NUM=1
CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y
CONFIG_SOC_TWAI_BRP_MIN=2 CONFIG_SOC_TWAI_BRP_MIN=2
CONFIG_SOC_TWAI_BRP_MAX=16384 CONFIG_SOC_TWAI_BRP_MAX=16384
...@@ -248,6 +254,8 @@ CONFIG_SOC_UART_SUPPORT_RTC_CLK=y ...@@ -248,6 +254,8 @@ CONFIG_SOC_UART_SUPPORT_RTC_CLK=y
CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y
CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y
CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y
CONFIG_SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE=y
CONFIG_SOC_UHCI_NUM=1
CONFIG_SOC_COEX_HW_PTI=y CONFIG_SOC_COEX_HW_PTI=y
CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21 CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21
CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192 CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192
...@@ -267,6 +275,7 @@ CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y ...@@ -267,6 +275,7 @@ CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y
CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y
CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y
CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y
CONFIG_SOC_CLK_LP_FAST_SUPPORT_XTAL_D2=y
CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y
CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL=y CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL=y
CONFIG_SOC_WIFI_HW_TSF=y CONFIG_SOC_WIFI_HW_TSF=y
...@@ -316,6 +325,17 @@ CONFIG_BOOTLOADER_COMPILE_TIME_DATE=y ...@@ -316,6 +325,17 @@ CONFIG_BOOTLOADER_COMPILE_TIME_DATE=y
CONFIG_BOOTLOADER_PROJECT_VER=1 CONFIG_BOOTLOADER_PROJECT_VER=1
# end of Bootloader manager # end of Bootloader manager
#
# Application Rollback
#
# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set
# end of Application Rollback
#
# Bootloader Rollback
#
# end of Bootloader Rollback
CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0 CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set
...@@ -325,6 +345,8 @@ CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y ...@@ -325,6 +345,8 @@ CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
# #
# Log # Log
# #
CONFIG_BOOTLOADER_LOG_VERSION_1=y
CONFIG_BOOTLOADER_LOG_VERSION=1
# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set # CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set # CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set # CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set
...@@ -339,6 +361,13 @@ CONFIG_BOOTLOADER_LOG_LEVEL=3 ...@@ -339,6 +361,13 @@ CONFIG_BOOTLOADER_LOG_LEVEL=3
# CONFIG_BOOTLOADER_LOG_COLORS is not set # CONFIG_BOOTLOADER_LOG_COLORS is not set
CONFIG_BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS=y CONFIG_BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS=y
# end of Format # end of Format
#
# Settings
#
CONFIG_BOOTLOADER_LOG_MODE_TEXT_EN=y
CONFIG_BOOTLOADER_LOG_MODE_TEXT=y
# end of Settings
# end of Log # end of Log
# #
...@@ -354,7 +383,6 @@ CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y ...@@ -354,7 +383,6 @@ CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y
CONFIG_BOOTLOADER_WDT_ENABLE=y CONFIG_BOOTLOADER_WDT_ENABLE=y
# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set # CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set
CONFIG_BOOTLOADER_WDT_TIME_MS=9000 CONFIG_BOOTLOADER_WDT_TIME_MS=9000
# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set
# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set # CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set
# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set # CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set
# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set # CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set
...@@ -396,6 +424,7 @@ CONFIG_ESP_ROM_GET_CLK_FREQ=y ...@@ -396,6 +424,7 @@ CONFIG_ESP_ROM_GET_CLK_FREQ=y
CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y
CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y
CONFIG_ESP_ROM_HAS_SPI_FLASH=y CONFIG_ESP_ROM_HAS_SPI_FLASH=y
CONFIG_ESP_ROM_HAS_SPI_FLASH_MMAP=y
CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y
CONFIG_ESP_ROM_HAS_NEWLIB=y CONFIG_ESP_ROM_HAS_NEWLIB=y
CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y
...@@ -406,6 +435,8 @@ CONFIG_ESP_ROM_HAS_SW_FLOAT=y ...@@ -406,6 +435,8 @@ CONFIG_ESP_ROM_HAS_SW_FLOAT=y
CONFIG_ESP_ROM_USB_OTG_NUM=-1 CONFIG_ESP_ROM_USB_OTG_NUM=-1
CONFIG_ESP_ROM_HAS_VERSION=y CONFIG_ESP_ROM_HAS_VERSION=y
CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB=y CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB=y
CONFIG_ESP_ROM_CONSOLE_OUTPUT_SECONDARY=y
CONFIG_ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY=y
# #
# Boot ROM Behavior # Boot ROM Behavior
...@@ -471,12 +502,10 @@ CONFIG_ENV_GPIO_RANGE_MIN=0 ...@@ -471,12 +502,10 @@ CONFIG_ENV_GPIO_RANGE_MIN=0
CONFIG_ENV_GPIO_RANGE_MAX=19 CONFIG_ENV_GPIO_RANGE_MAX=19
CONFIG_ENV_GPIO_IN_RANGE_MAX=19 CONFIG_ENV_GPIO_IN_RANGE_MAX=19
CONFIG_ENV_GPIO_OUT_RANGE_MAX=19 CONFIG_ENV_GPIO_OUT_RANGE_MAX=19
# CONFIG_BLINK_LED_GPIO is not set CONFIG_BLINK_LED_GPIO=y
CONFIG_BLINK_LED_STRIP=y # CONFIG_BLINK_LED_STRIP is not set
CONFIG_BLINK_LED_STRIP_BACKEND_RMT=y
# CONFIG_BLINK_LED_STRIP_BACKEND_SPI is not set
CONFIG_BLINK_GPIO=8 CONFIG_BLINK_GPIO=8
CONFIG_BLINK_PERIOD=1000 CONFIG_BLINK_PERIOD=100
# end of Example Configuration # end of Example Configuration
# #
...@@ -554,11 +583,11 @@ CONFIG_APPTRACE_LOCK_ENABLE=y ...@@ -554,11 +583,11 @@ CONFIG_APPTRACE_LOCK_ENABLE=y
# #
# #
# TWAI Configuration # Legacy TWAI Driver Configurations
# #
# CONFIG_TWAI_ISR_IN_IRAM is not set # CONFIG_TWAI_SKIP_LEGACY_CONFLICT_CHECK is not set
CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y
# end of TWAI Configuration # end of Legacy TWAI Driver Configurations
# #
# Legacy ADC Driver Configuration # Legacy ADC Driver Configuration
...@@ -627,6 +656,7 @@ CONFIG_EFUSE_MAX_BLK_LEN=256 ...@@ -627,6 +656,7 @@ CONFIG_EFUSE_MAX_BLK_LEN=256
# ESP-TLS # ESP-TLS
# #
CONFIG_ESP_TLS_USING_MBEDTLS=y CONFIG_ESP_TLS_USING_MBEDTLS=y
# CONFIG_ESP_TLS_USE_SECURE_ELEMENT is not set
CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y
# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set # CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set
# CONFIG_ESP_TLS_SERVER_SESSION_TICKETS is not set # CONFIG_ESP_TLS_SERVER_SESSION_TICKETS is not set
...@@ -671,7 +701,7 @@ CONFIG_ESP_ERR_TO_NAME_LOOKUP=y ...@@ -671,7 +701,7 @@ CONFIG_ESP_ERR_TO_NAME_LOOKUP=y
# #
CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM=y CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM=y
# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set # CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set
# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set # CONFIG_GPTIMER_ISR_CACHE_SAFE is not set
CONFIG_GPTIMER_OBJ_CACHE_SAFE=y CONFIG_GPTIMER_OBJ_CACHE_SAFE=y
# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set # CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set
# end of ESP-Driver:GPTimer Configurations # end of ESP-Driver:GPTimer Configurations
...@@ -682,6 +712,7 @@ CONFIG_GPTIMER_OBJ_CACHE_SAFE=y ...@@ -682,6 +712,7 @@ CONFIG_GPTIMER_OBJ_CACHE_SAFE=y
# CONFIG_I2C_ISR_IRAM_SAFE is not set # CONFIG_I2C_ISR_IRAM_SAFE is not set
# CONFIG_I2C_ENABLE_DEBUG_LOG is not set # CONFIG_I2C_ENABLE_DEBUG_LOG is not set
# CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2 is not set # CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2 is not set
CONFIG_I2C_MASTER_ISR_HANDLER_IN_IRAM=y
# end of ESP-Driver:I2C Configurations # end of ESP-Driver:I2C Configurations
# #
...@@ -700,9 +731,15 @@ CONFIG_GPTIMER_OBJ_CACHE_SAFE=y ...@@ -700,9 +731,15 @@ CONFIG_GPTIMER_OBJ_CACHE_SAFE=y
# #
# ESP-Driver:RMT Configurations # ESP-Driver:RMT Configurations
# #
# CONFIG_RMT_ISR_IRAM_SAFE is not set CONFIG_RMT_ENCODER_FUNC_IN_IRAM=y
CONFIG_RMT_TX_ISR_HANDLER_IN_IRAM=y
CONFIG_RMT_RX_ISR_HANDLER_IN_IRAM=y
# CONFIG_RMT_RECV_FUNC_IN_IRAM is not set # CONFIG_RMT_RECV_FUNC_IN_IRAM is not set
# CONFIG_RMT_TX_ISR_CACHE_SAFE is not set
# CONFIG_RMT_RX_ISR_CACHE_SAFE is not set
CONFIG_RMT_OBJ_CACHE_SAFE=y
# CONFIG_RMT_ENABLE_DEBUG_LOG is not set # CONFIG_RMT_ENABLE_DEBUG_LOG is not set
# CONFIG_RMT_ISR_IRAM_SAFE is not set
# end of ESP-Driver:RMT Configurations # end of ESP-Driver:RMT Configurations
# #
...@@ -727,12 +764,28 @@ CONFIG_SPI_SLAVE_ISR_IN_IRAM=y ...@@ -727,12 +764,28 @@ CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set # CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set
# end of ESP-Driver:Temperature Sensor Configurations # end of ESP-Driver:Temperature Sensor Configurations
#
# ESP-Driver:TWAI Configurations
#
# CONFIG_TWAI_ISR_IN_IRAM is not set
# CONFIG_TWAI_ISR_CACHE_SAFE is not set
# CONFIG_TWAI_ENABLE_DEBUG_LOG is not set
# end of ESP-Driver:TWAI Configurations
# #
# ESP-Driver:UART Configurations # ESP-Driver:UART Configurations
# #
# CONFIG_UART_ISR_IN_IRAM is not set # CONFIG_UART_ISR_IN_IRAM is not set
# end of ESP-Driver:UART Configurations # end of ESP-Driver:UART Configurations
#
# ESP-Driver:UHCI Configurations
#
# CONFIG_UHCI_ISR_HANDLER_IN_IRAM is not set
# CONFIG_UHCI_ISR_CACHE_SAFE is not set
# CONFIG_UHCI_ENABLE_DEBUG_LOG is not set
# end of ESP-Driver:UHCI Configurations
# #
# ESP-Driver:USB Serial/JTAG Configuration # ESP-Driver:USB Serial/JTAG Configuration
# #
...@@ -811,6 +864,7 @@ CONFIG_ESP_HTTPS_OTA_EVENT_POST_TIMEOUT=2000 ...@@ -811,6 +864,7 @@ CONFIG_ESP_HTTPS_OTA_EVENT_POST_TIMEOUT=2000
# #
# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set # CONFIG_ESP_HTTPS_SERVER_ENABLE is not set
CONFIG_ESP_HTTPS_SERVER_EVENT_POST_TIMEOUT=2000 CONFIG_ESP_HTTPS_SERVER_EVENT_POST_TIMEOUT=2000
# CONFIG_ESP_HTTPS_SERVER_CERT_SELECT_HOOK is not set
# end of ESP HTTPS server # end of ESP HTTPS server
# #
...@@ -883,15 +937,18 @@ CONFIG_RTC_CLK_CAL_CYCLES=1024 ...@@ -883,15 +937,18 @@ CONFIG_RTC_CLK_CAL_CYCLES=1024
# #
# Peripheral Control # Peripheral Control
# #
# CONFIG_PERIPH_CTRL_FUNC_IN_IRAM is not set CONFIG_ESP_PERIPH_CTRL_FUNC_IN_IRAM=y
CONFIG_ESP_REGI2C_CTRL_FUNC_IN_IRAM=y
# end of Peripheral Control # end of Peripheral Control
# #
# GDMA Configurations # GDMA Configurations
# #
CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y
# CONFIG_GDMA_ISR_IRAM_SAFE is not set CONFIG_GDMA_ISR_HANDLER_IN_IRAM=y
CONFIG_GDMA_OBJ_DRAM_SAFE=y
# CONFIG_GDMA_ENABLE_DEBUG_LOG is not set # CONFIG_GDMA_ENABLE_DEBUG_LOG is not set
# CONFIG_GDMA_ISR_IRAM_SAFE is not set
# end of GDMA Configurations # end of GDMA Configurations
# #
...@@ -901,7 +958,27 @@ CONFIG_XTAL_FREQ_40=y ...@@ -901,7 +958,27 @@ CONFIG_XTAL_FREQ_40=y
CONFIG_XTAL_FREQ=40 CONFIG_XTAL_FREQ=40
# end of Main XTAL Config # end of Main XTAL Config
#
# Power Supplier
#
#
# Brownout Detector
#
CONFIG_ESP_BROWNOUT_DET=y
CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set
CONFIG_ESP_BROWNOUT_DET_LVL=7
CONFIG_ESP_BROWNOUT_USE_INTR=y
# end of Brownout Detector
# end of Power Supplier
CONFIG_ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM=y CONFIG_ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM=y
CONFIG_ESP_INTR_IN_IRAM=y
# end of Hardware Settings # end of Hardware Settings
# #
...@@ -952,13 +1029,15 @@ CONFIG_ESP_PHY_RF_CAL_PARTIAL=y ...@@ -952,13 +1029,15 @@ CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
CONFIG_ESP_PHY_CALIBRATION_MODE=0 CONFIG_ESP_PHY_CALIBRATION_MODE=0
# CONFIG_ESP_PHY_PLL_TRACK_DEBUG is not set # CONFIG_ESP_PHY_PLL_TRACK_DEBUG is not set
# CONFIG_ESP_PHY_RECORD_USED_TIME is not set # CONFIG_ESP_PHY_RECORD_USED_TIME is not set
CONFIG_ESP_PHY_IRAM_OPT=y
# end of PHY # end of PHY
# #
# Power Management # Power Management
# #
CONFIG_PM_SLEEP_FUNC_IN_IRAM=y
# CONFIG_PM_ENABLE is not set # CONFIG_PM_ENABLE is not set
# CONFIG_PM_SLP_IRAM_OPT is not set CONFIG_PM_SLP_IRAM_OPT=y
CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
# end of Power Management # end of Power Management
...@@ -972,6 +1051,12 @@ CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y ...@@ -972,6 +1051,12 @@ CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
# end of ESP Ringbuf # end of ESP Ringbuf
#
# ESP-ROM
#
CONFIG_ESP_ROM_PRINT_IN_IRAM=y
# end of ESP-ROM
# #
# ESP Security Specific # ESP Security Specific
# #
...@@ -991,7 +1076,9 @@ CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0 ...@@ -991,7 +1076,9 @@ CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0
CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y
CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y
CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
CONFIG_ESP_SYSTEM_NO_BACKTRACE=y
# CONFIG_ESP_SYSTEM_USE_EH_FRAME is not set # CONFIG_ESP_SYSTEM_USE_EH_FRAME is not set
# CONFIG_ESP_SYSTEM_USE_FRAME_POINTER is not set
# #
# Memory protection # Memory protection
...@@ -1029,21 +1116,6 @@ CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y ...@@ -1029,21 +1116,6 @@ CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set # CONFIG_ESP_DEBUG_STUBS_ENABLE is not set
CONFIG_ESP_DEBUG_OCDAWARE=y CONFIG_ESP_DEBUG_OCDAWARE=y
CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y
#
# Brownout Detector
#
CONFIG_ESP_BROWNOUT_DET=y
CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set
CONFIG_ESP_BROWNOUT_DET_LVL=7
# end of Brownout Detector
CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
CONFIG_ESP_SYSTEM_HW_STACK_GUARD=y CONFIG_ESP_SYSTEM_HW_STACK_GUARD=y
CONFIG_ESP_SYSTEM_HW_PC_RECORD=y CONFIG_ESP_SYSTEM_HW_PC_RECORD=y
# end of ESP System Settings # end of ESP System Settings
...@@ -1057,6 +1129,7 @@ CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 ...@@ -1057,6 +1129,7 @@ CONFIG_ESP_IPC_TASK_STACK_SIZE=1024
# #
# ESP Timer (High Resolution Timer) # ESP Timer (High Resolution Timer)
# #
CONFIG_ESP_TIMER_IN_IRAM=y
# CONFIG_ESP_TIMER_PROFILING is not set # CONFIG_ESP_TIMER_PROFILING is not set
CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y
CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y
...@@ -1097,10 +1170,12 @@ CONFIG_ESP_WIFI_IRAM_OPT=y ...@@ -1097,10 +1170,12 @@ CONFIG_ESP_WIFI_IRAM_OPT=y
CONFIG_ESP_WIFI_RX_IRAM_OPT=y CONFIG_ESP_WIFI_RX_IRAM_OPT=y
CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
CONFIG_ESP_WIFI_ENABLE_SAE_PK=y CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
CONFIG_ESP_WIFI_ENABLE_SAE_H2E=y
CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y
CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y
# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set
CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME=50 CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME=50
# CONFIG_ESP_WIFI_BSS_MAX_IDLE_SUPPORT is not set
CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME=10 CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME=10
CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME=15 CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME=15
# CONFIG_ESP_WIFI_FTM_ENABLE is not set # CONFIG_ESP_WIFI_FTM_ENABLE is not set
...@@ -1261,6 +1336,7 @@ CONFIG_FREERTOS_DEBUG_OCDAWARE=y ...@@ -1261,6 +1336,7 @@ CONFIG_FREERTOS_DEBUG_OCDAWARE=y
CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH=y CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH=y
CONFIG_FREERTOS_NUMBER_OF_CORES=1 CONFIG_FREERTOS_NUMBER_OF_CORES=1
CONFIG_FREERTOS_IN_IRAM=y
# end of FreeRTOS # end of FreeRTOS
# #
...@@ -1271,8 +1347,6 @@ CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y ...@@ -1271,8 +1347,6 @@ CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
# CONFIG_HAL_ASSERTION_SILENT is not set # CONFIG_HAL_ASSERTION_SILENT is not set
# CONFIG_HAL_ASSERTION_ENABLE is not set # CONFIG_HAL_ASSERTION_ENABLE is not set
CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2 CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2
CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y
CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y
# end of Hardware Abstraction Layer (HAL) and Low Level (LL) # end of Hardware Abstraction Layer (HAL) and Low Level (LL)
# #
...@@ -1293,6 +1367,9 @@ CONFIG_HEAP_TRACING_OFF=y ...@@ -1293,6 +1367,9 @@ CONFIG_HEAP_TRACING_OFF=y
# #
# Log # Log
# #
CONFIG_LOG_VERSION_1=y
# CONFIG_LOG_VERSION_2 is not set
CONFIG_LOG_VERSION=1
# #
# Log Level # Log Level
...@@ -1330,6 +1407,15 @@ CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_SIZE=31 ...@@ -1330,6 +1407,15 @@ CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_SIZE=31
CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set # CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set
# end of Format # end of Format
#
# Settings
#
CONFIG_LOG_MODE_TEXT_EN=y
CONFIG_LOG_MODE_TEXT=y
# end of Settings
CONFIG_LOG_IN_IRAM=y
# end of Log # end of Log
# #
...@@ -1337,7 +1423,6 @@ CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y ...@@ -1337,7 +1423,6 @@ CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
# #
CONFIG_LWIP_ENABLE=y CONFIG_LWIP_ENABLE=y
CONFIG_LWIP_LOCAL_HOSTNAME="espressif" CONFIG_LWIP_LOCAL_HOSTNAME="espressif"
# CONFIG_LWIP_NETIF_API is not set
CONFIG_LWIP_TCPIP_TASK_PRIO=18 CONFIG_LWIP_TCPIP_TASK_PRIO=18
# CONFIG_LWIP_TCPIP_CORE_LOCKING is not set # CONFIG_LWIP_TCPIP_CORE_LOCKING is not set
# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set # CONFIG_LWIP_CHECK_THREAD_SAFETY is not set
...@@ -1482,6 +1567,7 @@ CONFIG_LWIP_DNS_MAX_HOST_IP=1 ...@@ -1482,6 +1567,7 @@ CONFIG_LWIP_DNS_MAX_HOST_IP=1
CONFIG_LWIP_DNS_MAX_SERVERS=3 CONFIG_LWIP_DNS_MAX_SERVERS=3
# CONFIG_LWIP_FALLBACK_DNS_SERVER_SUPPORT is not set # CONFIG_LWIP_FALLBACK_DNS_SERVER_SUPPORT is not set
# CONFIG_LWIP_DNS_SETSERVER_WITH_NETIF is not set # CONFIG_LWIP_DNS_SETSERVER_WITH_NETIF is not set
# CONFIG_LWIP_USE_ESP_GETADDRINFO is not set
# end of DNS # end of DNS
CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7 CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7
...@@ -1502,6 +1588,9 @@ CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y ...@@ -1502,6 +1588,9 @@ CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y
CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y
# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set # CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set
# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set # CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set
CONFIG_LWIP_HOOK_DHCP_EXTRA_OPTION_NONE=y
# CONFIG_LWIP_HOOK_DHCP_EXTRA_OPTION_DEFAULT is not set
# CONFIG_LWIP_HOOK_DHCP_EXTRA_OPTION_CUSTOM is not set
CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y
# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set
# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set
...@@ -1650,6 +1739,7 @@ CONFIG_MBEDTLS_ECP_NIST_OPTIM=y ...@@ -1650,6 +1739,7 @@ CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
# CONFIG_MBEDTLS_THREADING_C is not set # CONFIG_MBEDTLS_THREADING_C is not set
CONFIG_MBEDTLS_ERROR_STRINGS=y CONFIG_MBEDTLS_ERROR_STRINGS=y
CONFIG_MBEDTLS_FS_IO=y CONFIG_MBEDTLS_FS_IO=y
# CONFIG_MBEDTLS_ALLOW_WEAK_CERTIFICATE_VERIFICATION is not set
# end of mbedTLS # end of mbedTLS
# #
...@@ -1669,20 +1759,24 @@ CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y ...@@ -1669,20 +1759,24 @@ CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
# end of ESP-MQTT Configurations # end of ESP-MQTT Configurations
# #
# Newlib # LibC
# #
CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y CONFIG_LIBC_NEWLIB=y
# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set CONFIG_LIBC_MISC_IN_IRAM=y
# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set CONFIG_LIBC_LOCKS_PLACE_IN_IRAM=y
# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set CONFIG_LIBC_STDOUT_LINE_ENDING_CRLF=y
# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set # CONFIG_LIBC_STDOUT_LINE_ENDING_LF is not set
CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y # CONFIG_LIBC_STDOUT_LINE_ENDING_CR is not set
# CONFIG_NEWLIB_NANO_FORMAT is not set # CONFIG_LIBC_STDIN_LINE_ENDING_CRLF is not set
CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y # CONFIG_LIBC_STDIN_LINE_ENDING_LF is not set
# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set CONFIG_LIBC_STDIN_LINE_ENDING_CR=y
# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set # CONFIG_LIBC_NEWLIB_NANO_FORMAT is not set
# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT=y
# end of Newlib # CONFIG_LIBC_TIME_SYSCALL_USE_RTC is not set
# CONFIG_LIBC_TIME_SYSCALL_USE_HRT is not set
# CONFIG_LIBC_TIME_SYSCALL_USE_NONE is not set
# CONFIG_LIBC_OPTIMIZED_MISALIGNED_ACCESS is not set
# end of LibC
# #
# NVS # NVS
...@@ -1753,6 +1847,7 @@ CONFIG_SPI_FLASH_BROWNOUT_RESET=y ...@@ -1753,6 +1847,7 @@ CONFIG_SPI_FLASH_BROWNOUT_RESET=y
CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US=50 CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US=50
# CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND is not set # CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND is not set
# CONFIG_SPI_FLASH_FORCE_ENABLE_C6_H2_SUSPEND is not set # CONFIG_SPI_FLASH_FORCE_ENABLE_C6_H2_SUSPEND is not set
CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM=y
# end of Optional and Experimental Features (READ DOCS FIRST) # end of Optional and Experimental Features (READ DOCS FIRST)
# end of Main Flash configuration # end of Main Flash configuration
...@@ -1855,6 +1950,7 @@ CONFIG_UNITY_ENABLE_DOUBLE=y ...@@ -1855,6 +1950,7 @@ CONFIG_UNITY_ENABLE_DOUBLE=y
CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
# CONFIG_UNITY_ENABLE_FIXTURE is not set # CONFIG_UNITY_ENABLE_FIXTURE is not set
# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set # CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set
# CONFIG_UNITY_TEST_ORDER_BY_FILE_PATH_AND_LINE is not set
# end of Unity unit testing library # end of Unity unit testing library
# #
...@@ -1900,6 +1996,7 @@ CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y ...@@ -1900,6 +1996,7 @@ CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y
# Deprecated options for backward compatibility # Deprecated options for backward compatibility
# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set # CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
# CONFIG_NO_BLOBS is not set # CONFIG_NO_BLOBS is not set
# CONFIG_APP_ROLLBACK_ENABLE is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set # CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set # CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set # CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
...@@ -1907,7 +2004,6 @@ CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y ...@@ -1907,7 +2004,6 @@ CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y
# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set # CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set # CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set
CONFIG_LOG_BOOTLOADER_LEVEL=3 CONFIG_LOG_BOOTLOADER_LEVEL=3
# CONFIG_APP_ROLLBACK_ENABLE is not set
# CONFIG_FLASH_ENCRYPTION_ENABLED is not set # CONFIG_FLASH_ENCRYPTION_ENABLED is not set
# CONFIG_FLASHMODE_QIO is not set # CONFIG_FLASHMODE_QIO is not set
# CONFIG_FLASHMODE_QOUT is not set # CONFIG_FLASHMODE_QOUT is not set
...@@ -1934,6 +2030,7 @@ CONFIG_ESP32_APPTRACE_DEST_NONE=y ...@@ -1934,6 +2030,7 @@ CONFIG_ESP32_APPTRACE_DEST_NONE=y
CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
# CONFIG_EXTERNAL_COEX_ENABLE is not set # CONFIG_EXTERNAL_COEX_ENABLE is not set
# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set # CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set
# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set
# CONFIG_EVENT_LOOP_PROFILING is not set # CONFIG_EVENT_LOOP_PROFILING is not set
CONFIG_POST_EVENTS_FROM_ISR=y CONFIG_POST_EVENTS_FROM_ISR=y
CONFIG_POST_EVENTS_FROM_IRAM_ISR=y CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
...@@ -1947,6 +2044,24 @@ CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC=y ...@@ -1947,6 +2044,24 @@ CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC=y
# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC is not set # CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 is not set # CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES=1024 CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES=1024
CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y
CONFIG_BROWNOUT_DET=y
CONFIG_ESP32C3_BROWNOUT_DET=y
CONFIG_BROWNOUT_DET_LVL_SEL_7=y
CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7=y
# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2 is not set
CONFIG_BROWNOUT_DET_LVL=7
CONFIG_ESP32C3_BROWNOUT_DET_LVL=7
CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
...@@ -1978,22 +2093,6 @@ CONFIG_TASK_WDT_TIMEOUT_S=5 ...@@ -1978,22 +2093,6 @@ CONFIG_TASK_WDT_TIMEOUT_S=5
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set # CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
CONFIG_ESP32C3_DEBUG_OCDAWARE=y CONFIG_ESP32C3_DEBUG_OCDAWARE=y
CONFIG_BROWNOUT_DET=y
CONFIG_ESP32C3_BROWNOUT_DET=y
CONFIG_BROWNOUT_DET_LVL_SEL_7=y
CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7=y
# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2 is not set
CONFIG_BROWNOUT_DET_LVL=7
CONFIG_ESP32C3_BROWNOUT_DET_LVL=7
CONFIG_IPC_TASK_STACK_SIZE=1024 CONFIG_IPC_TASK_STACK_SIZE=1024
CONFIG_TIMER_TASK_STACK_SIZE=3584 CONFIG_TIMER_TASK_STACK_SIZE=3584
CONFIG_ESP32_WIFI_ENABLED=y CONFIG_ESP32_WIFI_ENABLED=y
...@@ -2056,9 +2155,20 @@ CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y ...@@ -2056,9 +2155,20 @@ CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set # CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set
CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
# CONFIG_PPP_SUPPORT is not set # CONFIG_PPP_SUPPORT is not set
CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set
# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set
# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set
# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set
CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
# CONFIG_NEWLIB_NANO_FORMAT is not set
CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y
CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER=y CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER=y
# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set
# CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC is not set # CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC is not set
# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set
# CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER is not set # CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER is not set
# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set
# CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE is not set # CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE is not set
CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
......
# #
# Automatically generated file. DO NOT EDIT. # Automatically generated file. DO NOT EDIT.
# Espressif IoT Development Framework (ESP-IDF) 5.4.1 Project Configuration # Espressif IoT Development Framework (ESP-IDF) 5.5.0 Project Configuration
# #
CONFIG_SOC_ADC_SUPPORTED=y CONFIG_SOC_ADC_SUPPORTED=y
CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y
CONFIG_SOC_UART_SUPPORTED=y CONFIG_SOC_UART_SUPPORTED=y
CONFIG_SOC_GDMA_SUPPORTED=y CONFIG_SOC_GDMA_SUPPORTED=y
CONFIG_SOC_UHCI_SUPPORTED=y
CONFIG_SOC_AHB_GDMA_SUPPORTED=y CONFIG_SOC_AHB_GDMA_SUPPORTED=y
CONFIG_SOC_GPTIMER_SUPPORTED=y CONFIG_SOC_GPTIMER_SUPPORTED=y
CONFIG_SOC_PHY_SUPPORTED=y CONFIG_SOC_TWAI_SUPPORTED=y
CONFIG_SOC_BT_SUPPORTED=y CONFIG_SOC_BT_SUPPORTED=y
CONFIG_SOC_WIFI_SUPPORTED=y
CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y
CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y
CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y
CONFIG_SOC_XT_WDT_SUPPORTED=y
CONFIG_SOC_PHY_SUPPORTED=y
CONFIG_SOC_WIFI_SUPPORTED=y
CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y
CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK=y CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y
CONFIG_SOC_EFUSE_HAS_EFUSE_RST_BUG=y
CONFIG_SOC_EFUSE_SUPPORTED=y CONFIG_SOC_EFUSE_SUPPORTED=y
CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y
CONFIG_SOC_RTC_MEM_SUPPORTED=y
CONFIG_SOC_I2S_SUPPORTED=y
CONFIG_SOC_RMT_SUPPORTED=y
CONFIG_SOC_SDM_SUPPORTED=y
CONFIG_SOC_GPSPI_SUPPORTED=y
CONFIG_SOC_LEDC_SUPPORTED=y CONFIG_SOC_LEDC_SUPPORTED=y
CONFIG_SOC_I2C_SUPPORTED=y CONFIG_SOC_I2C_SUPPORTED=y
CONFIG_SOC_GPSPI_SUPPORTED=y CONFIG_SOC_SYSTIMER_SUPPORTED=y
CONFIG_SOC_SUPPORT_COEXISTENCE=y
CONFIG_SOC_AES_SUPPORTED=y
CONFIG_SOC_MPI_SUPPORTED=y
CONFIG_SOC_SHA_SUPPORTED=y CONFIG_SOC_SHA_SUPPORTED=y
CONFIG_SOC_ECC_SUPPORTED=y CONFIG_SOC_HMAC_SUPPORTED=y
CONFIG_SOC_DIG_SIGN_SUPPORTED=y
CONFIG_SOC_FLASH_ENC_SUPPORTED=y CONFIG_SOC_FLASH_ENC_SUPPORTED=y
CONFIG_SOC_SECURE_BOOT_SUPPORTED=y CONFIG_SOC_SECURE_BOOT_SUPPORTED=y
CONFIG_SOC_SYSTIMER_SUPPORTED=y CONFIG_SOC_MEMPROT_SUPPORTED=y
CONFIG_SOC_BOD_SUPPORTED=y CONFIG_SOC_BOD_SUPPORTED=y
CONFIG_SOC_CLK_TREE_SUPPORTED=y CONFIG_SOC_CLK_TREE_SUPPORTED=y
CONFIG_SOC_ASSIST_DEBUG_SUPPORTED=y CONFIG_SOC_ASSIST_DEBUG_SUPPORTED=y
...@@ -34,18 +49,25 @@ CONFIG_SOC_LIGHT_SLEEP_SUPPORTED=y ...@@ -34,18 +49,25 @@ CONFIG_SOC_LIGHT_SLEEP_SUPPORTED=y
CONFIG_SOC_DEEP_SLEEP_SUPPORTED=y CONFIG_SOC_DEEP_SLEEP_SUPPORTED=y
CONFIG_SOC_LP_PERIPH_SHARE_INTERRUPT=y CONFIG_SOC_LP_PERIPH_SHARE_INTERRUPT=y
CONFIG_SOC_PM_SUPPORTED=y CONFIG_SOC_PM_SUPPORTED=y
CONFIG_SOC_XTAL_SUPPORT_26M=y
CONFIG_SOC_XTAL_SUPPORT_40M=y CONFIG_SOC_XTAL_SUPPORT_40M=y
CONFIG_SOC_AES_SUPPORT_DMA=y
CONFIG_SOC_AES_GDMA=y
CONFIG_SOC_AES_SUPPORT_AES_128=y
CONFIG_SOC_AES_SUPPORT_AES_256=y
CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y
CONFIG_SOC_ADC_ARBITER_SUPPORTED=y
CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y
CONFIG_SOC_ADC_MONITOR_SUPPORTED=y CONFIG_SOC_ADC_MONITOR_SUPPORTED=y
CONFIG_SOC_ADC_PERIPH_NUM=1 CONFIG_SOC_ADC_DMA_SUPPORTED=y
CONFIG_SOC_ADC_PERIPH_NUM=2
CONFIG_SOC_ADC_MAX_CHANNEL_NUM=5 CONFIG_SOC_ADC_MAX_CHANNEL_NUM=5
CONFIG_SOC_ADC_ATTEN_NUM=4 CONFIG_SOC_ADC_ATTEN_NUM=4
CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=1 CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=1
CONFIG_SOC_ADC_PATT_LEN_MAX=8 CONFIG_SOC_ADC_PATT_LEN_MAX=8
CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12 CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12
CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12 CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12
CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4
CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4
CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2 CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2
CONFIG_SOC_ADC_DIGI_MONITOR_NUM=2 CONFIG_SOC_ADC_DIGI_MONITOR_NUM=2
CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333 CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333
...@@ -55,31 +77,35 @@ CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12 ...@@ -55,31 +77,35 @@ CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12
CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y
CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y
CONFIG_SOC_ADC_SHARED_POWER=y CONFIG_SOC_ADC_SHARED_POWER=y
CONFIG_SOC_APB_BACKUP_DMA=y
CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y
CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y
CONFIG_SOC_CACHE_FREEZE_SUPPORTED=y
CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE=0x4000
CONFIG_SOC_CPU_CORES_NUM=1 CONFIG_SOC_CPU_CORES_NUM=1
CONFIG_SOC_CPU_INTR_NUM=32 CONFIG_SOC_CPU_INTR_NUM=32
CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC=y CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC=y
CONFIG_SOC_CPU_HAS_CSR_PC=y CONFIG_SOC_CPU_HAS_CSR_PC=y
CONFIG_SOC_CPU_BREAKPOINTS_NUM=2 CONFIG_SOC_CPU_BREAKPOINTS_NUM=8
CONFIG_SOC_CPU_WATCHPOINTS_NUM=2 CONFIG_SOC_CPU_WATCHPOINTS_NUM=8
CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE=0x80000000 CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE=0x80000000
CONFIG_SOC_CPU_IDRAM_SPLIT_USING_PMP=y CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=3072
CONFIG_SOC_ECC_SUPPORT_POINT_VERIFY_QUIRK=y CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16
CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100
CONFIG_SOC_AHB_GDMA_VERSION=1 CONFIG_SOC_AHB_GDMA_VERSION=1
CONFIG_SOC_GDMA_NUM_GROUPS_MAX=1 CONFIG_SOC_GDMA_NUM_GROUPS_MAX=1
CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX=1 CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX=3
CONFIG_SOC_GPIO_PORT=1 CONFIG_SOC_GPIO_PORT=1
CONFIG_SOC_GPIO_PIN_COUNT=21 CONFIG_SOC_GPIO_PIN_COUNT=22
CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y
CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y
CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y
CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP=y CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP=y
CONFIG_SOC_GPIO_IN_RANGE_MAX=20 CONFIG_SOC_GPIO_IN_RANGE_MAX=21
CONFIG_SOC_GPIO_OUT_RANGE_MAX=20 CONFIG_SOC_GPIO_OUT_RANGE_MAX=21
CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK=0 CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK=0
CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT=6 CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT=6
CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x00000000001FFFC0 CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x00000000003FFFC0
CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX=y CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX=y
CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM=3 CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM=3
CONFIG_SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP=y CONFIG_SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP=y
...@@ -88,30 +114,70 @@ CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8 ...@@ -88,30 +114,70 @@ CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8
CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE=y CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE=y
CONFIG_SOC_I2C_NUM=1 CONFIG_SOC_I2C_NUM=1
CONFIG_SOC_HP_I2C_NUM=1 CONFIG_SOC_HP_I2C_NUM=1
CONFIG_SOC_I2C_FIFO_LEN=16 CONFIG_SOC_I2C_FIFO_LEN=32
CONFIG_SOC_I2C_CMD_REG_NUM=8 CONFIG_SOC_I2C_CMD_REG_NUM=8
CONFIG_SOC_I2C_SUPPORT_SLAVE=y
CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y
CONFIG_SOC_I2C_SUPPORT_XTAL=y CONFIG_SOC_I2C_SUPPORT_XTAL=y
CONFIG_SOC_I2C_SUPPORT_RTC=y CONFIG_SOC_I2C_SUPPORT_RTC=y
CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR=y CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR=y
CONFIG_SOC_LEDC_SUPPORT_PLL_DIV_CLOCK=y CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST=y
CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE=y
CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS=y
CONFIG_SOC_I2S_NUM=1
CONFIG_SOC_I2S_HW_VERSION_2=y
CONFIG_SOC_I2S_SUPPORTS_XTAL=y
CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y
CONFIG_SOC_I2S_SUPPORTS_PCM=y
CONFIG_SOC_I2S_SUPPORTS_PDM=y
CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y
CONFIG_SOC_I2S_SUPPORTS_PCM2PDM=y
CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y
CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2
CONFIG_SOC_I2S_PDM_MAX_RX_LINES=1
CONFIG_SOC_I2S_SUPPORTS_TDM=y
CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y
CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y
CONFIG_SOC_LEDC_TIMER_NUM=4 CONFIG_SOC_LEDC_TIMER_NUM=4
CONFIG_SOC_LEDC_CHANNEL_NUM=6 CONFIG_SOC_LEDC_CHANNEL_NUM=6
CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14 CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14
CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y
CONFIG_SOC_MMU_PAGE_SIZE_CONFIGURABLE=y
CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1 CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1
CONFIG_SOC_MMU_PERIPH_NUM=1 CONFIG_SOC_MMU_PERIPH_NUM=1
CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000 CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000
CONFIG_SOC_MPU_REGIONS_MAX_NUM=8 CONFIG_SOC_MPU_REGIONS_MAX_NUM=8
CONFIG_SOC_RMT_GROUPS=1
CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=2
CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=2
CONFIG_SOC_RMT_CHANNELS_PER_GROUP=4
CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48
CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y
CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y
CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y
CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y
CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y
CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y
CONFIG_SOC_RMT_SUPPORT_XTAL=y
CONFIG_SOC_RMT_SUPPORT_APB=y
CONFIG_SOC_RMT_SUPPORT_RC_FAST=y
CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128 CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128
CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=108 CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=108
CONFIG_SOC_SLEEP_SYSTIMER_STALL_WORKAROUND=y
CONFIG_SOC_SLEEP_TGWDT_STOP_WORKAROUND=y
CONFIG_SOC_RTCIO_PIN_COUNT=0 CONFIG_SOC_RTCIO_PIN_COUNT=0
CONFIG_SOC_MPI_MEM_BLOCKS_NUM=4
CONFIG_SOC_MPI_OPERATIONS_NUM=3
CONFIG_SOC_RSA_MAX_BIT_LEN=3072
CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968
CONFIG_SOC_SHA_SUPPORT_DMA=y
CONFIG_SOC_SHA_SUPPORT_RESUME=y CONFIG_SOC_SHA_SUPPORT_RESUME=y
CONFIG_SOC_SHA_GDMA=y
CONFIG_SOC_SHA_SUPPORT_SHA1=y CONFIG_SOC_SHA_SUPPORT_SHA1=y
CONFIG_SOC_SHA_SUPPORT_SHA224=y CONFIG_SOC_SHA_SUPPORT_SHA224=y
CONFIG_SOC_SHA_SUPPORT_SHA256=y CONFIG_SOC_SHA_SUPPORT_SHA256=y
CONFIG_SOC_SDM_GROUPS=1
CONFIG_SOC_SDM_CHANNELS_PER_GROUP=4
CONFIG_SOC_SDM_CLK_SUPPORT_APB=y
CONFIG_SOC_SPI_PERIPH_NUM=2 CONFIG_SOC_SPI_PERIPH_NUM=2
CONFIG_SOC_SPI_MAX_CS_NUM=6 CONFIG_SOC_SPI_MAX_CS_NUM=6
CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64 CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64
...@@ -120,8 +186,8 @@ CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y ...@@ -120,8 +186,8 @@ CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y
CONFIG_SOC_SPI_SUPPORT_CD_SIG=y CONFIG_SOC_SPI_SUPPORT_CD_SIG=y
CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y
CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y
CONFIG_SOC_SPI_SUPPORT_CLK_APB=y
CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y
CONFIG_SOC_SPI_SUPPORT_CLK_PLL_F40M=y
CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y
CONFIG_SOC_SPI_SCT_SUPPORTED=y CONFIG_SOC_SPI_SCT_SUPPORTED=y
CONFIG_SOC_SPI_SCT_REG_NUM=14 CONFIG_SOC_SPI_SCT_REG_NUM=14
...@@ -135,11 +201,12 @@ CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y ...@@ -135,11 +201,12 @@ CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y
CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR=y CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR=y
CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y
CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS=y CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS=y
CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y
CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y
CONFIG_SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED=y CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y
CONFIG_SOC_MEMSPI_SRC_FREQ_30M_SUPPORTED=y CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y
CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED=y
CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y
CONFIG_SOC_MEMSPI_SRC_FREQ_15M_SUPPORTED=y
CONFIG_SOC_SYSTIMER_COUNTER_NUM=2 CONFIG_SOC_SYSTIMER_COUNTER_NUM=2
CONFIG_SOC_SYSTIMER_ALARM_NUM=3 CONFIG_SOC_SYSTIMER_ALARM_NUM=3
CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32 CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32
...@@ -147,67 +214,93 @@ CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20 ...@@ -147,67 +214,93 @@ CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20
CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y
CONFIG_SOC_SYSTIMER_INT_LEVEL=y CONFIG_SOC_SYSTIMER_INT_LEVEL=y
CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y
CONFIG_SOC_TIMER_GROUPS=1 CONFIG_SOC_TIMER_GROUPS=2
CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=1 CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=1
CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54 CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54
CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y
CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=1 CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y
CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=2
CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO=32 CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO=32
CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI=16 CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI=16
CONFIG_SOC_MWDT_SUPPORT_XTAL=y CONFIG_SOC_MWDT_SUPPORT_XTAL=y
CONFIG_SOC_TWAI_CONTROLLER_NUM=1
CONFIG_SOC_TWAI_MASK_FILTER_NUM=1
CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y
CONFIG_SOC_TWAI_BRP_MIN=2
CONFIG_SOC_TWAI_BRP_MAX=16384
CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y
CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y
CONFIG_SOC_EFUSE_DIS_PAD_JTAG=y CONFIG_SOC_EFUSE_DIS_PAD_JTAG=y
CONFIG_SOC_EFUSE_DIS_USB_JTAG=y
CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y
CONFIG_SOC_SECURE_BOOT_V2_ECC=y CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y
CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=1 CONFIG_SOC_EFUSE_DIS_ICACHE=y
CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y
CONFIG_SOC_SECURE_BOOT_V2_RSA=y
CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3
CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y
CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y
CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32 CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32
CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y
CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS=y
CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y
CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED=y CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16
CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=512
CONFIG_SOC_UART_NUM=2 CONFIG_SOC_UART_NUM=2
CONFIG_SOC_UART_HP_NUM=2 CONFIG_SOC_UART_HP_NUM=2
CONFIG_SOC_UART_FIFO_LEN=128 CONFIG_SOC_UART_FIFO_LEN=128
CONFIG_SOC_UART_BITRATE_MAX=2500000 CONFIG_SOC_UART_BITRATE_MAX=5000000
CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y CONFIG_SOC_UART_SUPPORT_APB_CLK=y
CONFIG_SOC_UART_SUPPORT_PLL_F40M_CLK=y
CONFIG_SOC_UART_SUPPORT_RTC_CLK=y CONFIG_SOC_UART_SUPPORT_RTC_CLK=y
CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y
CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y
CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y
CONFIG_SOC_SUPPORT_COEXISTENCE=y CONFIG_SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE=y
CONFIG_SOC_UHCI_NUM=1
CONFIG_SOC_COEX_HW_PTI=y CONFIG_SOC_COEX_HW_PTI=y
CONFIG_SOC_EXTERNAL_COEX_ADVANCE=y
CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21 CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21
CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192
CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12 CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12
CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y
CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y
CONFIG_SOC_PM_SUPPORT_CPU_PD=y
CONFIG_SOC_PM_SUPPORT_WIFI_PD=y
CONFIG_SOC_PM_SUPPORT_BT_PD=y
CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y
CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y
CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y
CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL=y
CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA=y
CONFIG_SOC_PM_MODEM_PD_BY_SW=y
CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y
CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y
CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y
CONFIG_SOC_CLK_OSC_SLOW_SUPPORTED=y CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y
CONFIG_SOC_CLK_LP_FAST_SUPPORT_XTAL_D2=y
CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y
CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL=y
CONFIG_SOC_WIFI_HW_TSF=y CONFIG_SOC_WIFI_HW_TSF=y
CONFIG_SOC_WIFI_FTM_SUPPORT=y CONFIG_SOC_WIFI_FTM_SUPPORT=y
CONFIG_SOC_WIFI_GCMP_SUPPORT=y
CONFIG_SOC_WIFI_WAPI_SUPPORT=y
CONFIG_SOC_WIFI_CSI_SUPPORT=y
CONFIG_SOC_WIFI_MESH_SUPPORT=y
CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y
CONFIG_SOC_WIFI_PHY_NEEDS_USB_WORKAROUND=y CONFIG_SOC_WIFI_PHY_NEEDS_USB_WORKAROUND=y
CONFIG_SOC_BLE_SUPPORTED=y CONFIG_SOC_BLE_SUPPORTED=y
CONFIG_SOC_ESP_NIMBLE_CONTROLLER=y CONFIG_SOC_BLE_MESH_SUPPORTED=y
CONFIG_SOC_BLE_50_SUPPORTED=y CONFIG_SOC_BLE_50_SUPPORTED=y
CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y
CONFIG_SOC_BLUFI_SUPPORTED=y CONFIG_SOC_BLUFI_SUPPORTED=y
CONFIG_SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED=y
CONFIG_SOC_PHY_IMPROVE_RX_11B=y
CONFIG_SOC_PHY_COMBO_MODULE=y CONFIG_SOC_PHY_COMBO_MODULE=y
CONFIG_IDF_CMAKE=y CONFIG_IDF_CMAKE=y
CONFIG_IDF_TOOLCHAIN="gcc" CONFIG_IDF_TOOLCHAIN="gcc"
CONFIG_IDF_TOOLCHAIN_GCC=y CONFIG_IDF_TOOLCHAIN_GCC=y
CONFIG_IDF_TARGET_ARCH_RISCV=y CONFIG_IDF_TARGET_ARCH_RISCV=y
CONFIG_IDF_TARGET_ARCH="riscv" CONFIG_IDF_TARGET_ARCH="riscv"
CONFIG_IDF_TARGET="esp32c2" CONFIG_IDF_TARGET="esp32c3"
CONFIG_IDF_INIT_VERSION="5.4.1" CONFIG_IDF_INIT_VERSION="5.4.1"
CONFIG_IDF_TARGET_ESP32C2=y CONFIG_IDF_TARGET_ESP32C3=y
CONFIG_IDF_FIRMWARE_CHIP_ID=0x000C CONFIG_IDF_FIRMWARE_CHIP_ID=0x0005
# #
# Build type # Build type
...@@ -232,6 +325,17 @@ CONFIG_BOOTLOADER_COMPILE_TIME_DATE=y ...@@ -232,6 +325,17 @@ CONFIG_BOOTLOADER_COMPILE_TIME_DATE=y
CONFIG_BOOTLOADER_PROJECT_VER=1 CONFIG_BOOTLOADER_PROJECT_VER=1
# end of Bootloader manager # end of Bootloader manager
#
# Application Rollback
#
# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set
# end of Application Rollback
#
# Bootloader Rollback
#
# end of Bootloader Rollback
CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0 CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set
...@@ -241,6 +345,8 @@ CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y ...@@ -241,6 +345,8 @@ CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
# #
# Log # Log
# #
CONFIG_BOOTLOADER_LOG_VERSION_1=y
CONFIG_BOOTLOADER_LOG_VERSION=1
# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set # CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set # CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set # CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set
...@@ -255,6 +361,13 @@ CONFIG_BOOTLOADER_LOG_LEVEL=3 ...@@ -255,6 +361,13 @@ CONFIG_BOOTLOADER_LOG_LEVEL=3
# CONFIG_BOOTLOADER_LOG_COLORS is not set # CONFIG_BOOTLOADER_LOG_COLORS is not set
CONFIG_BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS=y CONFIG_BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS=y
# end of Format # end of Format
#
# Settings
#
CONFIG_BOOTLOADER_LOG_MODE_TEXT_EN=y
CONFIG_BOOTLOADER_LOG_MODE_TEXT=y
# end of Settings
# end of Log # end of Log
# #
...@@ -270,16 +383,17 @@ CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y ...@@ -270,16 +383,17 @@ CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y
CONFIG_BOOTLOADER_WDT_ENABLE=y CONFIG_BOOTLOADER_WDT_ENABLE=y
# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set # CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set
CONFIG_BOOTLOADER_WDT_TIME_MS=9000 CONFIG_BOOTLOADER_WDT_TIME_MS=9000
# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set
# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set # CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set
# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set # CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set
# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set # CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set
CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0
# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set
# end of Bootloader config # end of Bootloader config
# #
# Security features # Security features
# #
CONFIG_SECURE_BOOT_V2_ECC_SUPPORTED=y CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y
CONFIG_SECURE_BOOT_V2_PREFERRED=y CONFIG_SECURE_BOOT_V2_PREFERRED=y
# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set # CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
# CONFIG_SECURE_BOOT is not set # CONFIG_SECURE_BOOT is not set
...@@ -299,28 +413,30 @@ CONFIG_APP_RETRIEVE_LEN_ELF_SHA=9 ...@@ -299,28 +413,30 @@ CONFIG_APP_RETRIEVE_LEN_ELF_SHA=9
CONFIG_ESP_ROM_HAS_CRC_LE=y CONFIG_ESP_ROM_HAS_CRC_LE=y
CONFIG_ESP_ROM_HAS_CRC_BE=y CONFIG_ESP_ROM_HAS_CRC_BE=y
CONFIG_ESP_ROM_HAS_MZ_CRC32=y
CONFIG_ESP_ROM_HAS_JPEG_DECODE=y
CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y
CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=3
CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y
CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y
CONFIG_ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV=y
CONFIG_ESP_ROM_GET_CLK_FREQ=y CONFIG_ESP_ROM_GET_CLK_FREQ=y
CONFIG_ESP_ROM_HAS_RVFPLIB=y CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y
CONFIG_ESP_ROM_HAS_HAL_WDT=y
CONFIG_ESP_ROM_HAS_HAL_SYSTIMER=y
CONFIG_ESP_ROM_HAS_HEAP_TLSF=y
CONFIG_ESP_ROM_TLSF_CHECK_PATCH=y
CONFIG_ESP_ROM_MULTI_HEAP_WALK_PATCH=y
CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y
CONFIG_ESP_ROM_HAS_SPI_FLASH=y CONFIG_ESP_ROM_HAS_SPI_FLASH=y
CONFIG_ESP_ROM_HAS_SPI_FLASH_MMAP=y
CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y
CONFIG_ESP_ROM_HAS_NEWLIB=y CONFIG_ESP_ROM_HAS_NEWLIB=y
CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y
CONFIG_ESP_ROM_HAS_NEWLIB_32BIT_TIME=y
CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y
CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y
CONFIG_ESP_ROM_HAS_MBEDTLS_CRYPTO_LIB=y
CONFIG_ESP_ROM_HAS_SW_FLOAT=y CONFIG_ESP_ROM_HAS_SW_FLOAT=y
CONFIG_ESP_ROM_USB_OTG_NUM=-1 CONFIG_ESP_ROM_USB_OTG_NUM=-1
CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=-1
CONFIG_ESP_ROM_HAS_VERSION=y CONFIG_ESP_ROM_HAS_VERSION=y
CONFIG_ESP_ROM_HAS_VPRINTF_FUNC=y CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB=y
CONFIG_ESP_ROM_HAS_OUTPUT_PUTC_FUNC=y CONFIG_ESP_ROM_CONSOLE_OUTPUT_SECONDARY=y
CONFIG_ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY=y
# #
# Boot ROM Behavior # Boot ROM Behavior
...@@ -341,11 +457,11 @@ CONFIG_ESPTOOLPY_FLASHMODE_DIO=y ...@@ -341,11 +457,11 @@ CONFIG_ESPTOOLPY_FLASHMODE_DIO=y
# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set # CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set
CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y
CONFIG_ESPTOOLPY_FLASHMODE="dio" CONFIG_ESPTOOLPY_FLASHMODE="dio"
CONFIG_ESPTOOLPY_FLASHFREQ_60M=y CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
# CONFIG_ESPTOOLPY_FLASHFREQ_30M is not set # CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set
# CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set
# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set # CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set
# CONFIG_ESPTOOLPY_FLASHFREQ_15M is not set CONFIG_ESPTOOLPY_FLASHFREQ="80m"
CONFIG_ESPTOOLPY_FLASHFREQ="60m"
# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set # CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set
CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y
# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set # CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set
...@@ -383,11 +499,13 @@ CONFIG_PARTITION_TABLE_MD5=y ...@@ -383,11 +499,13 @@ CONFIG_PARTITION_TABLE_MD5=y
# Example Configuration # Example Configuration
# #
CONFIG_ENV_GPIO_RANGE_MIN=0 CONFIG_ENV_GPIO_RANGE_MIN=0
CONFIG_ENV_GPIO_RANGE_MAX=18 CONFIG_ENV_GPIO_RANGE_MAX=19
CONFIG_ENV_GPIO_IN_RANGE_MAX=18 CONFIG_ENV_GPIO_IN_RANGE_MAX=19
CONFIG_ENV_GPIO_OUT_RANGE_MAX=18 CONFIG_ENV_GPIO_OUT_RANGE_MAX=19
CONFIG_BLINK_LED_GPIO=y # CONFIG_BLINK_LED_GPIO is not set
# CONFIG_BLINK_LED_STRIP is not set CONFIG_BLINK_LED_STRIP=y
CONFIG_BLINK_LED_STRIP_BACKEND_RMT=y
# CONFIG_BLINK_LED_STRIP_BACKEND_SPI is not set
CONFIG_BLINK_GPIO=8 CONFIG_BLINK_GPIO=8
CONFIG_BLINK_PERIOD=1000 CONFIG_BLINK_PERIOD=1000
# end of Example Configuration # end of Example Configuration
...@@ -403,8 +521,7 @@ CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y ...@@ -403,8 +521,7 @@ CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y
# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set
# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set
CONFIG_COMPILER_ASSERT_NDEBUG_EVALUATE=y CONFIG_COMPILER_ASSERT_NDEBUG_EVALUATE=y
# CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB is not set CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y
CONFIG_COMPILER_FLOAT_LIB_FROM_RVFPLIB=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2 CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2
# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set # CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
CONFIG_COMPILER_HIDE_PATHS_MACROS=y CONFIG_COMPILER_HIDE_PATHS_MACROS=y
...@@ -439,6 +556,7 @@ CONFIG_COMPILER_ORPHAN_SECTIONS_WARNING=y ...@@ -439,6 +556,7 @@ CONFIG_COMPILER_ORPHAN_SECTIONS_WARNING=y
# CONFIG_APPTRACE_DEST_JTAG is not set # CONFIG_APPTRACE_DEST_JTAG is not set
CONFIG_APPTRACE_DEST_NONE=y CONFIG_APPTRACE_DEST_NONE=y
# CONFIG_APPTRACE_DEST_UART1 is not set # CONFIG_APPTRACE_DEST_UART1 is not set
# CONFIG_APPTRACE_DEST_USB_CDC is not set
CONFIG_APPTRACE_DEST_UART_NONE=y CONFIG_APPTRACE_DEST_UART_NONE=y
CONFIG_APPTRACE_UART_TASK_PRIO=1 CONFIG_APPTRACE_UART_TASK_PRIO=1
CONFIG_APPTRACE_LOCK_ENABLE=y CONFIG_APPTRACE_LOCK_ENABLE=y
...@@ -466,6 +584,13 @@ CONFIG_APPTRACE_LOCK_ENABLE=y ...@@ -466,6 +584,13 @@ CONFIG_APPTRACE_LOCK_ENABLE=y
# Driver Configurations # Driver Configurations
# #
#
# Legacy TWAI Driver Configurations
#
# CONFIG_TWAI_SKIP_LEGACY_CONFLICT_CHECK is not set
CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y
# end of Legacy TWAI Driver Configurations
# #
# Legacy ADC Driver Configuration # Legacy ADC Driver Configuration
# #
...@@ -486,12 +611,33 @@ CONFIG_APPTRACE_LOCK_ENABLE=y ...@@ -486,12 +611,33 @@ CONFIG_APPTRACE_LOCK_ENABLE=y
# CONFIG_GPTIMER_SKIP_LEGACY_CONFLICT_CHECK is not set # CONFIG_GPTIMER_SKIP_LEGACY_CONFLICT_CHECK is not set
# end of Legacy Timer Group Driver Configurations # end of Legacy Timer Group Driver Configurations
#
# Legacy RMT Driver Configurations
#
# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set
# CONFIG_RMT_SKIP_LEGACY_CONFLICT_CHECK is not set
# end of Legacy RMT Driver Configurations
#
# Legacy I2S Driver Configurations
#
# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set
# CONFIG_I2S_SKIP_LEGACY_CONFLICT_CHECK is not set
# end of Legacy I2S Driver Configurations
# #
# Legacy I2C Driver Configurations # Legacy I2C Driver Configurations
# #
# CONFIG_I2C_SKIP_LEGACY_CONFLICT_CHECK is not set # CONFIG_I2C_SKIP_LEGACY_CONFLICT_CHECK is not set
# end of Legacy I2C Driver Configurations # end of Legacy I2C Driver Configurations
#
# Legacy SDM Driver Configurations
#
# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set
# CONFIG_SDM_SKIP_LEGACY_CONFLICT_CHECK is not set
# end of Legacy SDM Driver Configurations
# #
# Legacy Temperature Sensor Driver Configurations # Legacy Temperature Sensor Driver Configurations
# #
...@@ -512,6 +658,8 @@ CONFIG_EFUSE_MAX_BLK_LEN=256 ...@@ -512,6 +658,8 @@ CONFIG_EFUSE_MAX_BLK_LEN=256
# ESP-TLS # ESP-TLS
# #
CONFIG_ESP_TLS_USING_MBEDTLS=y CONFIG_ESP_TLS_USING_MBEDTLS=y
# CONFIG_ESP_TLS_USE_SECURE_ELEMENT is not set
CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y
# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set # CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set
# CONFIG_ESP_TLS_SERVER_SESSION_TICKETS is not set # CONFIG_ESP_TLS_SERVER_SESSION_TICKETS is not set
# CONFIG_ESP_TLS_SERVER_CERT_SELECT_HOOK is not set # CONFIG_ESP_TLS_SERVER_CERT_SELECT_HOOK is not set
...@@ -524,6 +672,9 @@ CONFIG_ESP_TLS_USING_MBEDTLS=y ...@@ -524,6 +672,9 @@ CONFIG_ESP_TLS_USING_MBEDTLS=y
# ADC and ADC Calibration # ADC and ADC Calibration
# #
# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set # CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set
# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set
# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set
# CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 is not set
# CONFIG_ADC_ENABLE_DEBUG_LOG is not set # CONFIG_ADC_ENABLE_DEBUG_LOG is not set
# end of ADC and ADC Calibration # end of ADC and ADC Calibration
...@@ -552,7 +703,7 @@ CONFIG_ESP_ERR_TO_NAME_LOOKUP=y ...@@ -552,7 +703,7 @@ CONFIG_ESP_ERR_TO_NAME_LOOKUP=y
# #
CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM=y CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM=y
# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set # CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set
# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set # CONFIG_GPTIMER_ISR_CACHE_SAFE is not set
CONFIG_GPTIMER_OBJ_CACHE_SAFE=y CONFIG_GPTIMER_OBJ_CACHE_SAFE=y
# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set # CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set
# end of ESP-Driver:GPTimer Configurations # end of ESP-Driver:GPTimer Configurations
...@@ -563,14 +714,43 @@ CONFIG_GPTIMER_OBJ_CACHE_SAFE=y ...@@ -563,14 +714,43 @@ CONFIG_GPTIMER_OBJ_CACHE_SAFE=y
# CONFIG_I2C_ISR_IRAM_SAFE is not set # CONFIG_I2C_ISR_IRAM_SAFE is not set
# CONFIG_I2C_ENABLE_DEBUG_LOG is not set # CONFIG_I2C_ENABLE_DEBUG_LOG is not set
# CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2 is not set # CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2 is not set
CONFIG_I2C_MASTER_ISR_HANDLER_IN_IRAM=y
# end of ESP-Driver:I2C Configurations # end of ESP-Driver:I2C Configurations
#
# ESP-Driver:I2S Configurations
#
# CONFIG_I2S_ISR_IRAM_SAFE is not set
# CONFIG_I2S_ENABLE_DEBUG_LOG is not set
# end of ESP-Driver:I2S Configurations
# #
# ESP-Driver:LEDC Configurations # ESP-Driver:LEDC Configurations
# #
# CONFIG_LEDC_CTRL_FUNC_IN_IRAM is not set # CONFIG_LEDC_CTRL_FUNC_IN_IRAM is not set
# end of ESP-Driver:LEDC Configurations # end of ESP-Driver:LEDC Configurations
#
# ESP-Driver:RMT Configurations
#
CONFIG_RMT_ENCODER_FUNC_IN_IRAM=y
CONFIG_RMT_TX_ISR_HANDLER_IN_IRAM=y
CONFIG_RMT_RX_ISR_HANDLER_IN_IRAM=y
# CONFIG_RMT_RECV_FUNC_IN_IRAM is not set
# CONFIG_RMT_TX_ISR_CACHE_SAFE is not set
# CONFIG_RMT_RX_ISR_CACHE_SAFE is not set
CONFIG_RMT_OBJ_CACHE_SAFE=y
# CONFIG_RMT_ENABLE_DEBUG_LOG is not set
# CONFIG_RMT_ISR_IRAM_SAFE is not set
# end of ESP-Driver:RMT Configurations
#
# ESP-Driver:Sigma Delta Modulator Configurations
#
# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set
# CONFIG_SDM_ENABLE_DEBUG_LOG is not set
# end of ESP-Driver:Sigma Delta Modulator Configurations
# #
# ESP-Driver:SPI Configurations # ESP-Driver:SPI Configurations
# #
...@@ -586,12 +766,34 @@ CONFIG_SPI_SLAVE_ISR_IN_IRAM=y ...@@ -586,12 +766,34 @@ CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set # CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set
# end of ESP-Driver:Temperature Sensor Configurations # end of ESP-Driver:Temperature Sensor Configurations
#
# ESP-Driver:TWAI Configurations
#
# CONFIG_TWAI_ISR_IN_IRAM is not set
# CONFIG_TWAI_ISR_CACHE_SAFE is not set
# CONFIG_TWAI_ENABLE_DEBUG_LOG is not set
# end of ESP-Driver:TWAI Configurations
# #
# ESP-Driver:UART Configurations # ESP-Driver:UART Configurations
# #
# CONFIG_UART_ISR_IN_IRAM is not set # CONFIG_UART_ISR_IN_IRAM is not set
# end of ESP-Driver:UART Configurations # end of ESP-Driver:UART Configurations
#
# ESP-Driver:UHCI Configurations
#
# CONFIG_UHCI_ISR_HANDLER_IN_IRAM is not set
# CONFIG_UHCI_ISR_CACHE_SAFE is not set
# CONFIG_UHCI_ENABLE_DEBUG_LOG is not set
# end of ESP-Driver:UHCI Configurations
#
# ESP-Driver:USB Serial/JTAG Configuration
#
CONFIG_USJ_ENABLE_USB_SERIAL_JTAG=y
# end of ESP-Driver:USB Serial/JTAG Configuration
# #
# Ethernet # Ethernet
# #
...@@ -664,6 +866,7 @@ CONFIG_ESP_HTTPS_OTA_EVENT_POST_TIMEOUT=2000 ...@@ -664,6 +866,7 @@ CONFIG_ESP_HTTPS_OTA_EVENT_POST_TIMEOUT=2000
# #
# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set # CONFIG_ESP_HTTPS_SERVER_ENABLE is not set
CONFIG_ESP_HTTPS_SERVER_EVENT_POST_TIMEOUT=2000 CONFIG_ESP_HTTPS_SERVER_EVENT_POST_TIMEOUT=2000
# CONFIG_ESP_HTTPS_SERVER_CERT_SELECT_HOOK is not set
# end of ESP HTTPS server # end of ESP HTTPS server
# #
...@@ -673,22 +876,25 @@ CONFIG_ESP_HTTPS_SERVER_EVENT_POST_TIMEOUT=2000 ...@@ -673,22 +876,25 @@ CONFIG_ESP_HTTPS_SERVER_EVENT_POST_TIMEOUT=2000
# #
# Chip revision # Chip revision
# #
CONFIG_ESP32C2_REV_MIN_1=y # CONFIG_ESP32C3_REV_MIN_0 is not set
# CONFIG_ESP32C2_REV_MIN_1_1 is not set # CONFIG_ESP32C3_REV_MIN_1 is not set
# CONFIG_ESP32C2_REV_MIN_200 is not set # CONFIG_ESP32C3_REV_MIN_2 is not set
CONFIG_ESP32C2_REV_MIN_FULL=100 CONFIG_ESP32C3_REV_MIN_3=y
CONFIG_ESP_REV_MIN_FULL=100 # CONFIG_ESP32C3_REV_MIN_4 is not set
# CONFIG_ESP32C3_REV_MIN_101 is not set
CONFIG_ESP32C3_REV_MIN_FULL=3
CONFIG_ESP_REV_MIN_FULL=3
# #
# Maximum Supported ESP32-C2 Revision (Rev v2.99) # Maximum Supported ESP32-C3 Revision (Rev v1.99)
# #
CONFIG_ESP32C2_REV_MAX_FULL=299 CONFIG_ESP32C3_REV_MAX_FULL=199
CONFIG_ESP_REV_MAX_FULL=299 CONFIG_ESP_REV_MAX_FULL=199
CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL=0 CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL=0
CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL=99 CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL=199
# #
# Maximum Supported ESP32-C2 eFuse Block Revision (eFuse Block Rev v0.99) # Maximum Supported ESP32-C3 eFuse Block Revision (eFuse Block Rev v1.99)
# #
# end of Chip revision # end of Chip revision
...@@ -701,9 +907,9 @@ CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y ...@@ -701,9 +907,9 @@ CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y
CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y
CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y
CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES=4 CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES=4
# CONFIG_ESP32C2_UNIVERSAL_MAC_ADDRESSES_TWO is not set # CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO is not set
CONFIG_ESP32C2_UNIVERSAL_MAC_ADDRESSES_FOUR=y CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR=y
CONFIG_ESP32C2_UNIVERSAL_MAC_ADDRESSES=4 CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES=4
# CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC is not set # CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC is not set
# end of MAC Config # end of MAC Config
...@@ -712,7 +918,7 @@ CONFIG_ESP32C2_UNIVERSAL_MAC_ADDRESSES=4 ...@@ -712,7 +918,7 @@ CONFIG_ESP32C2_UNIVERSAL_MAC_ADDRESSES=4
# #
# CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set # CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set
CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y
CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU=y # CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set
CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y
CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY=0 CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY=0
# CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION is not set # CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION is not set
...@@ -724,6 +930,7 @@ CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS=y ...@@ -724,6 +930,7 @@ CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS=y
# RTC Clock Config # RTC Clock Config
# #
CONFIG_RTC_CLK_SRC_INT_RC=y CONFIG_RTC_CLK_SRC_INT_RC=y
# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set # CONFIG_RTC_CLK_SRC_EXT_OSC is not set
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set # CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
CONFIG_RTC_CLK_CAL_CYCLES=1024 CONFIG_RTC_CLK_CAL_CYCLES=1024
...@@ -732,26 +939,48 @@ CONFIG_RTC_CLK_CAL_CYCLES=1024 ...@@ -732,26 +939,48 @@ CONFIG_RTC_CLK_CAL_CYCLES=1024
# #
# Peripheral Control # Peripheral Control
# #
# CONFIG_PERIPH_CTRL_FUNC_IN_IRAM is not set CONFIG_ESP_PERIPH_CTRL_FUNC_IN_IRAM=y
CONFIG_ESP_REGI2C_CTRL_FUNC_IN_IRAM=y
# end of Peripheral Control # end of Peripheral Control
# #
# GDMA Configurations # GDMA Configurations
# #
CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y
# CONFIG_GDMA_ISR_IRAM_SAFE is not set CONFIG_GDMA_ISR_HANDLER_IN_IRAM=y
CONFIG_GDMA_OBJ_DRAM_SAFE=y
# CONFIG_GDMA_ENABLE_DEBUG_LOG is not set # CONFIG_GDMA_ENABLE_DEBUG_LOG is not set
# CONFIG_GDMA_ISR_IRAM_SAFE is not set
# end of GDMA Configurations # end of GDMA Configurations
# #
# Main XTAL Config # Main XTAL Config
# #
# CONFIG_XTAL_FREQ_26 is not set
CONFIG_XTAL_FREQ_40=y CONFIG_XTAL_FREQ_40=y
CONFIG_XTAL_FREQ=40 CONFIG_XTAL_FREQ=40
# end of Main XTAL Config # end of Main XTAL Config
#
# Power Supplier
#
#
# Brownout Detector
#
CONFIG_ESP_BROWNOUT_DET=y
CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set
CONFIG_ESP_BROWNOUT_DET_LVL=7
CONFIG_ESP_BROWNOUT_USE_INTR=y
# end of Brownout Detector
# end of Power Supplier
CONFIG_ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM=y CONFIG_ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM=y
CONFIG_ESP_INTR_IN_IRAM=y
# end of Hardware Settings # end of Hardware Settings
# #
...@@ -794,22 +1023,24 @@ CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y ...@@ -794,22 +1023,24 @@ CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
CONFIG_ESP_PHY_MAX_TX_POWER=20 CONFIG_ESP_PHY_MAX_TX_POWER=20
# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set # CONFIG_ESP_PHY_REDUCE_TX_POWER is not set
# CONFIG_ESP_PHY_ENABLE_USB is not set CONFIG_ESP_PHY_ENABLE_USB=y
# CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set # CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set
CONFIG_ESP_PHY_RF_CAL_PARTIAL=y CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
# CONFIG_ESP_PHY_RF_CAL_NONE is not set # CONFIG_ESP_PHY_RF_CAL_NONE is not set
# CONFIG_ESP_PHY_RF_CAL_FULL is not set # CONFIG_ESP_PHY_RF_CAL_FULL is not set
CONFIG_ESP_PHY_CALIBRATION_MODE=0 CONFIG_ESP_PHY_CALIBRATION_MODE=0
# CONFIG_ESP_PHY_IMPROVE_RX_11B is not set
# CONFIG_ESP_PHY_PLL_TRACK_DEBUG is not set # CONFIG_ESP_PHY_PLL_TRACK_DEBUG is not set
# CONFIG_ESP_PHY_RECORD_USED_TIME is not set # CONFIG_ESP_PHY_RECORD_USED_TIME is not set
CONFIG_ESP_PHY_IRAM_OPT=y
# end of PHY # end of PHY
# #
# Power Management # Power Management
# #
CONFIG_PM_SLEEP_FUNC_IN_IRAM=y
# CONFIG_PM_ENABLE is not set # CONFIG_PM_ENABLE is not set
# CONFIG_PM_SLP_IRAM_OPT is not set CONFIG_PM_SLP_IRAM_OPT=y
CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
# end of Power Management # end of Power Management
# #
...@@ -822,6 +1053,12 @@ CONFIG_ESP_PHY_CALIBRATION_MODE=0 ...@@ -822,6 +1053,12 @@ CONFIG_ESP_PHY_CALIBRATION_MODE=0
# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
# end of ESP Ringbuf # end of ESP Ringbuf
#
# ESP-ROM
#
CONFIG_ESP_ROM_PRINT_IN_IRAM=y
# end of ESP-ROM
# #
# ESP Security Specific # ESP Security Specific
# #
...@@ -831,27 +1068,25 @@ CONFIG_ESP_PHY_CALIBRATION_MODE=0 ...@@ -831,27 +1068,25 @@ CONFIG_ESP_PHY_CALIBRATION_MODE=0
# ESP System Settings # ESP System Settings
# #
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set # CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_120=y CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=120 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
#
# Cache config
#
# CONFIG_ESP32C2_INSTRUCTION_CACHE_WRAP is not set
# end of Cache config
# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set # CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y
# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set # CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set
# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set # CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set
CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0 CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0
CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y
CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y
CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
CONFIG_ESP_SYSTEM_NO_BACKTRACE=y
# CONFIG_ESP_SYSTEM_USE_EH_FRAME is not set # CONFIG_ESP_SYSTEM_USE_EH_FRAME is not set
# CONFIG_ESP_SYSTEM_USE_FRAME_POINTER is not set
# #
# Memory protection # Memory protection
# #
CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT=y CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y
CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y
# end of Memory protection # end of Memory protection
CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32
...@@ -862,8 +1097,12 @@ CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y ...@@ -862,8 +1097,12 @@ CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y
CONFIG_ESP_MAIN_TASK_AFFINITY=0x0 CONFIG_ESP_MAIN_TASK_AFFINITY=0x0
CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048
CONFIG_ESP_CONSOLE_UART_DEFAULT=y CONFIG_ESP_CONSOLE_UART_DEFAULT=y
# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG is not set
# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set # CONFIG_ESP_CONSOLE_UART_CUSTOM is not set
# CONFIG_ESP_CONSOLE_NONE is not set # CONFIG_ESP_CONSOLE_NONE is not set
# CONFIG_ESP_CONSOLE_SECONDARY_NONE is not set
CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG=y
CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y
CONFIG_ESP_CONSOLE_UART=y CONFIG_ESP_CONSOLE_UART=y
CONFIG_ESP_CONSOLE_UART_NUM=0 CONFIG_ESP_CONSOLE_UART_NUM=0
CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM=0 CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM=0
...@@ -871,7 +1110,6 @@ CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 ...@@ -871,7 +1110,6 @@ CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200
CONFIG_ESP_INT_WDT=y CONFIG_ESP_INT_WDT=y
CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 CONFIG_ESP_INT_WDT_TIMEOUT_MS=300
CONFIG_ESP_TASK_WDT_EN=y CONFIG_ESP_TASK_WDT_EN=y
CONFIG_ESP_TASK_WDT_USE_ESP_TIMER=y
CONFIG_ESP_TASK_WDT_INIT=y CONFIG_ESP_TASK_WDT_INIT=y
# CONFIG_ESP_TASK_WDT_PANIC is not set # CONFIG_ESP_TASK_WDT_PANIC is not set
CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 CONFIG_ESP_TASK_WDT_TIMEOUT_S=5
...@@ -880,23 +1118,7 @@ CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y ...@@ -880,23 +1118,7 @@ CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set # CONFIG_ESP_DEBUG_STUBS_ENABLE is not set
CONFIG_ESP_DEBUG_OCDAWARE=y CONFIG_ESP_DEBUG_OCDAWARE=y
CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y
#
# Brownout Detector
#
CONFIG_ESP_BROWNOUT_DET=y
CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set
CONFIG_ESP_BROWNOUT_DET_LVL=7
# end of Brownout Detector
CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
CONFIG_ESP_SYSTEM_HW_STACK_GUARD=y CONFIG_ESP_SYSTEM_HW_STACK_GUARD=y
CONFIG_ESP_SYSTEM_BBPLL_RECALIB=y
CONFIG_ESP_SYSTEM_HW_PC_RECORD=y CONFIG_ESP_SYSTEM_HW_PC_RECORD=y
# end of ESP System Settings # end of ESP System Settings
...@@ -909,6 +1131,7 @@ CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 ...@@ -909,6 +1131,7 @@ CONFIG_ESP_IPC_TASK_STACK_SIZE=1024
# #
# ESP Timer (High Resolution Timer) # ESP Timer (High Resolution Timer)
# #
CONFIG_ESP_TIMER_IN_IRAM=y
# CONFIG_ESP_TIMER_PROFILING is not set # CONFIG_ESP_TIMER_PROFILING is not set
CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y
CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y
...@@ -918,7 +1141,7 @@ CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1 ...@@ -918,7 +1141,7 @@ CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1
CONFIG_ESP_TIMER_TASK_AFFINITY=0x0 CONFIG_ESP_TIMER_TASK_AFFINITY=0x0
CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y
CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y
CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD=y # CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set
CONFIG_ESP_TIMER_IMPL_SYSTIMER=y CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
# end of ESP Timer (High Resolution Timer) # end of ESP Timer (High Resolution Timer)
...@@ -936,6 +1159,7 @@ CONFIG_ESP_WIFI_STATIC_RX_MGMT_BUFFER=y ...@@ -936,6 +1159,7 @@ CONFIG_ESP_WIFI_STATIC_RX_MGMT_BUFFER=y
# CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUFFER is not set # CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUFFER is not set
CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUF=0 CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUF=0
CONFIG_ESP_WIFI_RX_MGMT_BUF_NUM_DEF=5 CONFIG_ESP_WIFI_RX_MGMT_BUF_NUM_DEF=5
# CONFIG_ESP_WIFI_CSI_ENABLED is not set
CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y
CONFIG_ESP_WIFI_TX_BA_WIN=6 CONFIG_ESP_WIFI_TX_BA_WIN=6
CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y
...@@ -948,20 +1172,25 @@ CONFIG_ESP_WIFI_IRAM_OPT=y ...@@ -948,20 +1172,25 @@ CONFIG_ESP_WIFI_IRAM_OPT=y
CONFIG_ESP_WIFI_RX_IRAM_OPT=y CONFIG_ESP_WIFI_RX_IRAM_OPT=y
CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
CONFIG_ESP_WIFI_ENABLE_SAE_PK=y CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
CONFIG_ESP_WIFI_ENABLE_SAE_H2E=y
CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y
CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y
# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set
CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME=50 CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME=50
# CONFIG_ESP_WIFI_BSS_MAX_IDLE_SUPPORT is not set
CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME=10 CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME=10
CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME=15 CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME=15
# CONFIG_ESP_WIFI_FTM_ENABLE is not set # CONFIG_ESP_WIFI_FTM_ENABLE is not set
CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE=y CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE=y
# CONFIG_ESP_WIFI_GCMP_SUPPORT is not set
CONFIG_ESP_WIFI_GMAC_SUPPORT=y CONFIG_ESP_WIFI_GMAC_SUPPORT=y
CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set # CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set
CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=2 CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7
CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y
CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
# CONFIG_ESP_WIFI_WAPI_PSK is not set
# CONFIG_ESP_WIFI_SUITE_B_192 is not set
# CONFIG_ESP_WIFI_11KV_SUPPORT is not set # CONFIG_ESP_WIFI_11KV_SUPPORT is not set
# CONFIG_ESP_WIFI_MBO_SUPPORT is not set # CONFIG_ESP_WIFI_MBO_SUPPORT is not set
# CONFIG_ESP_WIFI_DPP_SUPPORT is not set # CONFIG_ESP_WIFI_DPP_SUPPORT is not set
...@@ -978,7 +1207,7 @@ CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y ...@@ -978,7 +1207,7 @@ CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
# CONFIG_ESP_WIFI_DEBUG_PRINT is not set # CONFIG_ESP_WIFI_DEBUG_PRINT is not set
# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set # CONFIG_ESP_WIFI_TESTING_OPTIONS is not set
CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT=y CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT=y
CONFIG_ESP_WIFI_ENT_FREE_DYNAMIC_BUFFER=y # CONFIG_ESP_WIFI_ENT_FREE_DYNAMIC_BUFFER is not set
# end of Wi-Fi # end of Wi-Fi
# #
...@@ -1109,6 +1338,7 @@ CONFIG_FREERTOS_DEBUG_OCDAWARE=y ...@@ -1109,6 +1338,7 @@ CONFIG_FREERTOS_DEBUG_OCDAWARE=y
CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH=y CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH=y
CONFIG_FREERTOS_NUMBER_OF_CORES=1 CONFIG_FREERTOS_NUMBER_OF_CORES=1
CONFIG_FREERTOS_IN_IRAM=y
# end of FreeRTOS # end of FreeRTOS
# #
...@@ -1119,10 +1349,6 @@ CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y ...@@ -1119,10 +1349,6 @@ CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
# CONFIG_HAL_ASSERTION_SILENT is not set # CONFIG_HAL_ASSERTION_SILENT is not set
# CONFIG_HAL_ASSERTION_ENABLE is not set # CONFIG_HAL_ASSERTION_ENABLE is not set
CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2 CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2
CONFIG_HAL_SYSTIMER_USE_ROM_IMPL=y
CONFIG_HAL_WDT_USE_ROM_IMPL=y
CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y
CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y
# end of Hardware Abstraction Layer (HAL) and Low Level (LL) # end of Hardware Abstraction Layer (HAL) and Low Level (LL)
# #
...@@ -1137,12 +1363,15 @@ CONFIG_HEAP_TRACING_OFF=y ...@@ -1137,12 +1363,15 @@ CONFIG_HEAP_TRACING_OFF=y
# CONFIG_HEAP_USE_HOOKS is not set # CONFIG_HEAP_USE_HOOKS is not set
# CONFIG_HEAP_TASK_TRACKING is not set # CONFIG_HEAP_TASK_TRACKING is not set
# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set
CONFIG_HEAP_TLSF_USE_ROM_IMPL=y # CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set
# end of Heap memory debugging # end of Heap memory debugging
# #
# Log # Log
# #
CONFIG_LOG_VERSION_1=y
# CONFIG_LOG_VERSION_2 is not set
CONFIG_LOG_VERSION=1
# #
# Log Level # Log Level
...@@ -1180,6 +1409,15 @@ CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_SIZE=31 ...@@ -1180,6 +1409,15 @@ CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_SIZE=31
CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set # CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set
# end of Format # end of Format
#
# Settings
#
CONFIG_LOG_MODE_TEXT_EN=y
CONFIG_LOG_MODE_TEXT=y
# end of Settings
CONFIG_LOG_IN_IRAM=y
# end of Log # end of Log
# #
...@@ -1187,7 +1425,6 @@ CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y ...@@ -1187,7 +1425,6 @@ CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
# #
CONFIG_LWIP_ENABLE=y CONFIG_LWIP_ENABLE=y
CONFIG_LWIP_LOCAL_HOSTNAME="espressif" CONFIG_LWIP_LOCAL_HOSTNAME="espressif"
# CONFIG_LWIP_NETIF_API is not set
CONFIG_LWIP_TCPIP_TASK_PRIO=18 CONFIG_LWIP_TCPIP_TASK_PRIO=18
# CONFIG_LWIP_TCPIP_CORE_LOCKING is not set # CONFIG_LWIP_TCPIP_CORE_LOCKING is not set
# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set # CONFIG_LWIP_CHECK_THREAD_SAFETY is not set
...@@ -1332,6 +1569,7 @@ CONFIG_LWIP_DNS_MAX_HOST_IP=1 ...@@ -1332,6 +1569,7 @@ CONFIG_LWIP_DNS_MAX_HOST_IP=1
CONFIG_LWIP_DNS_MAX_SERVERS=3 CONFIG_LWIP_DNS_MAX_SERVERS=3
# CONFIG_LWIP_FALLBACK_DNS_SERVER_SUPPORT is not set # CONFIG_LWIP_FALLBACK_DNS_SERVER_SUPPORT is not set
# CONFIG_LWIP_DNS_SETSERVER_WITH_NETIF is not set # CONFIG_LWIP_DNS_SETSERVER_WITH_NETIF is not set
# CONFIG_LWIP_USE_ESP_GETADDRINFO is not set
# end of DNS # end of DNS
CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7 CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7
...@@ -1352,6 +1590,9 @@ CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y ...@@ -1352,6 +1590,9 @@ CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y
CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y
# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set # CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set
# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set # CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set
CONFIG_LWIP_HOOK_DHCP_EXTRA_OPTION_NONE=y
# CONFIG_LWIP_HOOK_DHCP_EXTRA_OPTION_DEFAULT is not set
# CONFIG_LWIP_HOOK_DHCP_EXTRA_OPTION_CUSTOM is not set
CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y
# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set
# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set
...@@ -1402,9 +1643,15 @@ CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200 ...@@ -1402,9 +1643,15 @@ CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200
# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set # CONFIG_MBEDTLS_ECP_RESTARTABLE is not set
CONFIG_MBEDTLS_CMAC_C=y CONFIG_MBEDTLS_CMAC_C=y
CONFIG_MBEDTLS_HARDWARE_AES=y
CONFIG_MBEDTLS_AES_USE_INTERRUPT=y
CONFIG_MBEDTLS_AES_INTERRUPT_LEVEL=0
CONFIG_MBEDTLS_GCM_SUPPORT_NON_AES_CIPHER=y
CONFIG_MBEDTLS_HARDWARE_MPI=y
CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI=y
CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y
CONFIG_MBEDTLS_MPI_INTERRUPT_LEVEL=0
CONFIG_MBEDTLS_HARDWARE_SHA=y CONFIG_MBEDTLS_HARDWARE_SHA=y
CONFIG_MBEDTLS_HARDWARE_ECC=y
CONFIG_MBEDTLS_ECC_OTHER_CURVES_SOFT_FALLBACK=y
CONFIG_MBEDTLS_ROM_MD5=y CONFIG_MBEDTLS_ROM_MD5=y
# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set # CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set # CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
...@@ -1493,8 +1740,8 @@ CONFIG_MBEDTLS_ECP_NIST_OPTIM=y ...@@ -1493,8 +1740,8 @@ CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
# CONFIG_MBEDTLS_HKDF_C is not set # CONFIG_MBEDTLS_HKDF_C is not set
# CONFIG_MBEDTLS_THREADING_C is not set # CONFIG_MBEDTLS_THREADING_C is not set
CONFIG_MBEDTLS_ERROR_STRINGS=y CONFIG_MBEDTLS_ERROR_STRINGS=y
# CONFIG_MBEDTLS_USE_CRYPTO_ROM_IMPL is not set
CONFIG_MBEDTLS_FS_IO=y CONFIG_MBEDTLS_FS_IO=y
# CONFIG_MBEDTLS_ALLOW_WEAK_CERTIFICATE_VERIFICATION is not set
# end of mbedTLS # end of mbedTLS
# #
...@@ -1514,24 +1761,29 @@ CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y ...@@ -1514,24 +1761,29 @@ CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
# end of ESP-MQTT Configurations # end of ESP-MQTT Configurations
# #
# Newlib # LibC
# #
CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y CONFIG_LIBC_NEWLIB=y
# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set CONFIG_LIBC_MISC_IN_IRAM=y
# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set CONFIG_LIBC_LOCKS_PLACE_IN_IRAM=y
# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set CONFIG_LIBC_STDOUT_LINE_ENDING_CRLF=y
# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set # CONFIG_LIBC_STDOUT_LINE_ENDING_LF is not set
CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y # CONFIG_LIBC_STDOUT_LINE_ENDING_CR is not set
CONFIG_NEWLIB_NANO_FORMAT=y # CONFIG_LIBC_STDIN_LINE_ENDING_CRLF is not set
CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y # CONFIG_LIBC_STDIN_LINE_ENDING_LF is not set
# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set CONFIG_LIBC_STDIN_LINE_ENDING_CR=y
# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set # CONFIG_LIBC_NEWLIB_NANO_FORMAT is not set
# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT=y
# end of Newlib # CONFIG_LIBC_TIME_SYSCALL_USE_RTC is not set
# CONFIG_LIBC_TIME_SYSCALL_USE_HRT is not set
# CONFIG_LIBC_TIME_SYSCALL_USE_NONE is not set
# CONFIG_LIBC_OPTIMIZED_MISALIGNED_ACCESS is not set
# end of LibC
# #
# NVS # NVS
# #
# CONFIG_NVS_ENCRYPTION is not set
# CONFIG_NVS_ASSERT_ERROR_CHECK is not set # CONFIG_NVS_ASSERT_ERROR_CHECK is not set
# CONFIG_NVS_LEGACY_DUP_KEYS_COMPATIBILITY is not set # CONFIG_NVS_LEGACY_DUP_KEYS_COMPATIBILITY is not set
# end of NVS # end of NVS
...@@ -1570,9 +1822,9 @@ CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" ...@@ -1570,9 +1822,9 @@ CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread"
# #
# MMU Config # MMU Config
# #
CONFIG_MMU_PAGE_SIZE_32KB=y CONFIG_MMU_PAGE_SIZE_64KB=y
CONFIG_MMU_PAGE_MODE="32KB" CONFIG_MMU_PAGE_MODE="64KB"
CONFIG_MMU_PAGE_SIZE=0x8000 CONFIG_MMU_PAGE_SIZE=0x10000
# end of MMU Config # end of MMU Config
# #
...@@ -1597,6 +1849,7 @@ CONFIG_SPI_FLASH_BROWNOUT_RESET=y ...@@ -1597,6 +1849,7 @@ CONFIG_SPI_FLASH_BROWNOUT_RESET=y
CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US=50 CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US=50
# CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND is not set # CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND is not set
# CONFIG_SPI_FLASH_FORCE_ENABLE_C6_H2_SUSPEND is not set # CONFIG_SPI_FLASH_FORCE_ENABLE_C6_H2_SUSPEND is not set
CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM=y
# end of Optional and Experimental Features (READ DOCS FIRST) # end of Optional and Experimental Features (READ DOCS FIRST)
# end of Main Flash configuration # end of Main Flash configuration
...@@ -1699,6 +1952,7 @@ CONFIG_UNITY_ENABLE_DOUBLE=y ...@@ -1699,6 +1952,7 @@ CONFIG_UNITY_ENABLE_DOUBLE=y
CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
# CONFIG_UNITY_ENABLE_FIXTURE is not set # CONFIG_UNITY_ENABLE_FIXTURE is not set
# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set # CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set
# CONFIG_UNITY_TEST_ORDER_BY_FILE_PATH_AND_LINE is not set
# end of Unity unit testing library # end of Unity unit testing library
# #
...@@ -1740,151 +1994,3 @@ CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y ...@@ -1740,151 +1994,3 @@ CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y
# end of Component config # end of Component config
# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set # CONFIG_IDF_EXPERIMENTAL_FEATURES is not set
# Deprecated options for backward compatibility
# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
# CONFIG_NO_BLOBS is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y
# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set
CONFIG_LOG_BOOTLOADER_LEVEL=3
# CONFIG_APP_ROLLBACK_ENABLE is not set
# CONFIG_FLASH_ENCRYPTION_ENABLED is not set
# CONFIG_FLASHMODE_QIO is not set
# CONFIG_FLASHMODE_QOUT is not set
CONFIG_FLASHMODE_DIO=y
# CONFIG_FLASHMODE_DOUT is not set
CONFIG_MONITOR_BAUD=115200
CONFIG_OPTIMIZATION_LEVEL_DEBUG=y
CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y
CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y
# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set
# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set
CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set
# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set
CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2
# CONFIG_CXX_EXCEPTIONS is not set
CONFIG_STACK_CHECK_NONE=y
# CONFIG_STACK_CHECK_NORM is not set
# CONFIG_STACK_CHECK_STRONG is not set
# CONFIG_STACK_CHECK_ALL is not set
# CONFIG_WARN_WRITE_STRINGS is not set
# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
CONFIG_ESP32_APPTRACE_DEST_NONE=y
CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
# CONFIG_EXTERNAL_COEX_ENABLE is not set
# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set
# CONFIG_EVENT_LOOP_PROFILING is not set
CONFIG_POST_EVENTS_FROM_ISR=y
CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
CONFIG_GDBSTUB_SUPPORT_TASKS=y
CONFIG_GDBSTUB_MAX_TASKS=32
# CONFIG_OTA_ALLOW_HTTP is not set
# CONFIG_ESP_SYSTEM_PD_FLASH is not set
CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
CONFIG_ESP32_PHY_MAX_TX_POWER=20
# CONFIG_REDUCE_PHY_TX_POWER is not set
# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set
CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
CONFIG_MAIN_TASK_STACK_SIZE=3584
CONFIG_CONSOLE_UART_DEFAULT=y
# CONFIG_CONSOLE_UART_CUSTOM is not set
# CONFIG_CONSOLE_UART_NONE is not set
# CONFIG_ESP_CONSOLE_UART_NONE is not set
CONFIG_CONSOLE_UART=y
CONFIG_CONSOLE_UART_NUM=0
CONFIG_CONSOLE_UART_BAUDRATE=115200
CONFIG_INT_WDT=y
CONFIG_INT_WDT_TIMEOUT_MS=300
CONFIG_TASK_WDT=y
CONFIG_ESP_TASK_WDT=y
# CONFIG_TASK_WDT_PANIC is not set
CONFIG_TASK_WDT_TIMEOUT_S=5
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
CONFIG_BROWNOUT_DET=y
CONFIG_BROWNOUT_DET_LVL_SEL_7=y
# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
CONFIG_BROWNOUT_DET_LVL=7
CONFIG_IPC_TASK_STACK_SIZE=1024
CONFIG_TIMER_TASK_STACK_SIZE=3584
CONFIG_ESP32_WIFI_ENABLED=y
CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y
CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1
CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32
CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
CONFIG_ESP32_WIFI_TX_BA_WIN=6
CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
CONFIG_ESP32_WIFI_RX_BA_WIN=6
CONFIG_ESP32_WIFI_NVS_ENABLED=y
CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
CONFIG_ESP32_WIFI_IRAM_OPT=y
CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y
CONFIG_WPA_MBEDTLS_CRYPTO=y
CONFIG_WPA_MBEDTLS_TLS_CLIENT=y
# CONFIG_WPA_11KV_SUPPORT is not set
# CONFIG_WPA_MBO_SUPPORT is not set
# CONFIG_WPA_DPP_SUPPORT is not set
# CONFIG_WPA_11R_SUPPORT is not set
# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set
# CONFIG_WPA_WPS_STRICT is not set
# CONFIG_WPA_DEBUG_PRINT is not set
# CONFIG_WPA_TESTING_OPTIONS is not set
# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
CONFIG_TIMER_TASK_PRIORITY=1
CONFIG_TIMER_TASK_STACK_DEPTH=2048
CONFIG_TIMER_QUEUE_LENGTH=10
# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
# CONFIG_HAL_ASSERTION_SILIENT is not set
# CONFIG_L2_TO_L3_COPY is not set
CONFIG_ESP_GRATUITOUS_ARP=y
CONFIG_GARP_TMR_INTERVAL=60
CONFIG_TCPIP_RECVMBOX_SIZE=32
CONFIG_TCP_MAXRTX=12
CONFIG_TCP_SYNMAXRTX=12
CONFIG_TCP_MSS=1440
CONFIG_TCP_MSL=60000
CONFIG_TCP_SND_BUF_DEFAULT=5760
CONFIG_TCP_WND_DEFAULT=5760
CONFIG_TCP_RECVMBOX_SIZE=6
CONFIG_TCP_QUEUE_OOSEQ=y
CONFIG_TCP_OVERSIZE_MSS=y
# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
# CONFIG_TCP_OVERSIZE_DISABLE is not set
CONFIG_UDP_RECVMBOX_SIZE=6
CONFIG_TCPIP_TASK_STACK_SIZE=3072
CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set
CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
# CONFIG_PPP_SUPPORT is not set
CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
CONFIG_ESP32_PTHREAD_STACK_MIN=768
CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1
CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set
# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set
CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
CONFIG_SUPPORT_TERMIOS=y
CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1
# End of deprecated options
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